## Via Inductance

I am receiving an increasing flurry of requests for information about via inductance. Presumably, those of you asking for such data have reached that level of speed where the inductance of a via becomes quite significant.

And what speed is that? Assuming an ordinary pcb thickness of 63 mils, the inductance of an ordinary via works out to only a few nanohenries, something that becomes increasingly significant at data rates in excess of 1 Gb/s.

The terrific pictures in this article come
from my new book, *High-Speed Signal Propagtion: Advanced Black Magic*,
an all-new sequel to (not just an update of) my earlier book *High-Speed Digital Design: A Handbook of Black Magic*. This note discusses the via-inductance formulas presented
in that book and relates them to other formulas and concepts you may have seen.

## Via Inductance

Rylan Luke of Rymar Engineering writes:

First, thanks both for your book, and the Mathcad files on your web site.

My question is about the parasitic inductance of vias. Shouldn't the effective length of the via be considered? For a recent 6 layer board, 63 mils total thickness, I calculated the inductance for a signal via connecting the two outer layers. The inductance of this via was 1.2nH. The inductance of a similar structure going only between the top layer trace and the first ground plane was markedly less, presumably due to the much smaller length of that via.

Is this a correct analysis?

You are correct that the length of the via affects its inductance. Not only the length of the via, but also the shape and proximity of the return-current path determines the inductance.

For example, let's work with a four-layer board having signal traces on layers 1 and 4 and solid reference planes on layers 2 and 3. Consider a signal via that dives through this board from top to bottom (1 to 4). Figure 1 illustrates this configuration, showing how at every point where high-frequency signal current flows, an equal and opposite current flows on the solid reference plane adjacent to the signal conductor.

Prior to encountering the via, returning signal current
associated with your layer-1 signal trace flows on the *top surface *of
layer 2, right underneath the signal trace on layer 1. The skin depth of copper
at high frequencies being much less than the thickness of a typical reference
plane, the return current actually flows only on the top surface of solid layer
2; it does not penetrate through that plane.

After traversing the signal via, your signal current appears on a trace located on layer 4. The return current at this point needs to flow on the bottom surface of layer 3 (the nearest surface to layer 4). How does the returning signal current get from layer 2 to layer 3? It can do so through vias IF THE PLANES CARRY THE SAME VOLTAGE, or through bypass capacitors if they do not.

Doesn't the returning signal current just pop between the planes through the parasitic capacitance of the planes themselves, you might ask? A complete answer to that question will have to wait for the next newsletter. The short answer is that in typical cases where the planes are widely spaced (as in a stripline cavity) the current seeks out the nearest metallic connection, such as a via or bypass capacitor, and follows that path.

I brought up the subject of returning signal currents because in order to calculate the inductance of a signal via you absolutely have to know where the returning signal current flows. This need arises because both the signal current and the returning signal current create magnetic fields. Inductance being nothing more than the temporary storage of energy in the form of a magnetic field, both fields must be calculated to determine the total inductance.

Next let's get down to the business of calculating the inductance of a signal via given a known pattern of inter-plane connections.

Assume one signal via and one inter-plane connection via, with the following parameters:

*s*- separation between vias, center-to-center-
*h*- separation between planes 2 and 3 (it doesn't matter if there are other unused reference planes in the way, all that matters is the aggregate spacing between the outermost reference planes traversed by the signal) -
*r*- radius of the via holes

Inductance is calculated for this configuration by assuming a current of 1 Amp flowing through the signal via and the same 1 Amp returning on the inter-plane connection. From this pattern of currents, one then calculates the magnetic field at all points inside the stripline cavity (between the planes). From this known magnetic field one then integrates, in the region between the vias, the total magnetic flux penetrating through a flat 2-D surface held vertically (like a curtain) and stretched from one via to the other, covering the entire stripline cavity from top to bottom. The total flux penetrating this 2-D surface equals the inductance. The procedure sounds laborious, I know, but it is how inductance calculations are done.

**Step 1: **The magnetic lines of force due to the
signal current form a set of concentric circles centered on the signal via. The
field strength is constant in the z-axis direction (parallel to the via). The
field falls off with 1/*x* as you move away from the via, with intensity

**Where:**

- is the magnetic permeability of free space, and
*x*is the radial distance in meters away from the signal via.

**Step 2:** The magnetic lines of force due to the
return current have the same profile, but centered around the position *s* of the return-current connection.

**Step 3: **Integrate the magnetic field between the
two vias. This step assumes that the signal and return vias are sufficiently far
apart that the existence of each via does not noticeably perturb the magnetic
field from the other.

The symmetrical arrangement of the vias suggests that the signal and return vias will contribute equal amounts of flux -- therefore we can just calculate the flux from the signal via and double it to get the result.

This is a two-dimensional integration. The first
integration (*dx*) goes horizontally across the curtain between the two
vias. The second integration works vertically from floor to ceiling (*z*=0
to *z*=*h*). Since the field is constant in the *z* dimension
this second integration merely multiplies the first result by a factor of *h*.

As the integrand in this expression involves 1/*x*,
the integrated result involves logarithms. The inductance represented by the
combination of one signal via and one return via at distance *s* equals:

In metric mks units (*h*, *s*, and *r* in
meters, *L* in Henries), the constant μ/2π works out to 2·10^{-7} H/m (assuming a non-magnetic dielectric). In English units, (*h*, *s*, and *r* in inches, *L* in nH) the constant μ/2π equals 5.08 nH/in.

**Other examples **are worked similarly. If the return
current is carried mainly on two vias equally spaced on either side of the
signal via, where the spacing from signal via to either return via is *s* and the via radius is *r*:

If the return current is carried mainly on four vias
equally spaced in a square pattern on four sides of the signal via, where the
spacing from signal via to any return via is *s* and the via radius is *r*:

If the return current is carried mainly on a coaxial
return path completely encircling the signal via, where the spacing from signal
via to the return path is *s* and the via radius is *r*:

The last formula I hope you will recognize as the
inductance of a short section of coaxial cable with length H and outer diameter
2*s*. I hope this recognition will lend credence to the idea that the
position of the returning current path is an important variable in the problem.

**Formula [7.9]**, page 259 in High-Speed Digital
Design, lists the inductance of a via as:

This formula for *L _{?}* is a gross approximation that
glosses over the position of the returning current path, a simplification I
greatly regret not making more clear in the book. It makes the crude assumption
that the return path is approximately coaxial and located at a distance

*s*=2

*eh*, where

*e*is the base used for natural logarithms. When the inductance really matters, a more accurate approximation is needed.

To see how formula [7.9] was derived, substitute 2*r* for the diameter *d*, and incorporate the additive factor of 1 inside the
logarithm as a multiplicative factor of *e*:

Comparing this to the formula [coax] shows the unwritten
assumption present within formula [7.9], namely that the return path is coaxial
and located at a distance of approximately *s*=2*eh* away from the
signal via.

If you are working with a 0.063-in. thick board with
eight-to-ten layers, the outer two solid planes are probably about 0.050 in.
apart. This height times 2*e* would be .2718 in. If you have a bunch of
return paths about this far away, that is the case approximation [7.9] was
intended to cover.

If you hold the position of the return paths constant and vary the inter-plane separation, the inductance changes linearly with inter-plane height (which equates roughly to via length).

If you modulate the position of the return paths at the
same time you vary the inter-plane height, always keeping *s*=2e*h*,
you get formula [7.9].

Note that all the approximations I have provided so far have the property that they give you the inductance of a via and its associated return path only covering that part of the via embedded between the planes. The part of the via that sticks up above the planes is not included. If you want to model that part (and I think that at today's speeds we are beginning to *need* that part), check out the models in my article: "Parasitic Inductance of Bypass Capacitors."

## MORE Via Inductance

Herbert Seidenberg at Conexant writes:

How do you reconcile that the inductance of a via is proportional to its length (page 259 of High-Speed Digital Design) and proportional to the square of its length in EDN, "Parasitic Inductance of Bypass Capacitors", July 20, 2000?

Thanks for your interest in High-Speed Digital Design.

That's the trouble with approximations, there are so many to choose from.

What you are seeing are two crude approximations that apply to two different situations.

In 3-dimensional space, as you move to a distance *x* away from a magnetic dipole, the fields spread out in an expanding sphere (whose
surface area grows with x-squared) so you get a field intensity that falls off inversely with x-squared.

In a 2-dimensional problem (such as a signal via and a
collection of return vias, with all the fields trapped between two big, solid
reference planes), the fields spread out radially from the signal (and return)
vias in expanding cylinders whose surface areas grow proportional to *x*,
so you get a field intensity that falls off inversely with x.

In the 2-dimensional problem (vias contained within two
reference planes), if I increase the height *h* between the planes by a
factor of *k* (essentially making the board *k* times thicker) then
each new, longer via generates *k* times the magnetic flux *all of which* is captured between the planes. In this situation inductance grows strictly in
proportion to height.

In the 3-dimensional problem (here I'm thinking about the partial stubs of the vias that stick up above the topmost reference plane), the magnetic fields are not trapped between two planes. The fields are free to spill all over the place in a full 3-D pattern. If you measure the total flux that falls under a particular trace, or under the body of a bypass capacitor, you are seeing an inductance that depends only upon a fraction of the total flux generated by that via.

In the 3-D case when you increase the length of the vias
two things happen: first, the vias create more total magnetic flux in proportion
to their new length, and second, the percentage of that flux that falls beneath
the associated trace (or bypass capacitor) goes up. The overall effect is an
increase in inductance proportional to the *square *of the length of the
part of the via that sticks up above the planes (which was the point of the July
20, 2000 article).

In the 3-D problem (vias sticking up above the reference planes) if you increase the via length to a ridiculous extent the space between the vias will eventually grow to the point where it accepts as big a fraction of the flux as it is ever going to get. Beyond this point the "increased proportion of flux" part of my argument evaporates, and you revert to an increase in inductance that scales merely in proportion to length, not length squared.

This transition from the 3-D behavior to the 2-D behavior corresponds to the "long and skinny" assumption often made in inductance approximations. That is, for an object sufficiently long and skinny we can ignore the fringing fields at the ends (that's the 3-D part) and just concentrate on the part in the middle, for which the field cross-section is uniform along the length of the object. The "long and skinny" assumption renders many problems more tractable. A classic example is the calculation of inductance between two long parallel wires. One normally ignores fringing fields at the ends of the wires in this problem, which leads to the conclusion that the inductance grows in direct proportion to the length of the wires. The via problem investigated in the July 20, 2000 article was so short that it was "all fringe" and "no middle", so the inductance developed a squared dependence on length.

Lastly, please beware that while the approximation on page 259 produces an answer with the right order of magnitude, it's not particularly accurate as it does not take into account details of the actual signal return path or the configuration of reference planes near the via.

## Even More Via Inductance

I couldn't resist throwing in one last picture while we are talking about via inductance. It shows the one configuration where via inductance is practically a non-issue. The signal trace in this example merely pops from one side of a solid plane to the other. Because in this scenario the returning signal current is not diverted away from the main body of the signal current, this configuration delivers better performance (i.e., less crosstalk and less emitted radiation) than any via that traverses multiple reference planes.

Microwave engineers who use extremely high frequencies and gigantic vias (100-mil holes and larger) will take things one step further by optimizing the length/diameter ratio of this via to balance its inductance and capacitance. If the get the L/C ratio equal to 2500, you've created a perfect 50-ohm through-connection from layer 1 to layer 3 that generates practically no reflections, and no additional crosstalk.

Best Regards,

Dr. Howard Johnson