## Parasitic Inductance of Bypass Capacitors

You can estimate the parasitic series inductance of a bypass capacitor in a multilayer board with solid power and ground planes. Use an approximation for the inductance L1 due to the chip layout Figure 1, green shaded region). Then, assuming that you have connected your chip and your bypass capacitor straight to the planes, use an approximation for the inductance L2 represented by the volume of magnetic flux trapped between the planes (blue region). Finally, you might want to consider the inductance, L3, of the chip package itself (red region). The internal details of the construction of a monolithic ceramic capacitor add little to the total inductance. The chip-package inductance (red region) is the least troublesome of the parts. Considering the chip's power and ground pins as a source of noise, the impedance of this source is much larger than the impedance between power and ground on your board. (If it were not, your board would have so much power-supply noise that it wouldn't work.) Therefore, the chip tends to act as a fixed source of current, independently of L3. In other words, L3 affects the power-and-ground bounce that your chip experiences but not the noise coupled onto the power and ground planes.

The chip power-supply currents flowing through the impedances of L2 and L1 generate most of the high-frequency power-and-ground-plane noise emanating from the structure in Figure 1. Power-and ground-plane noise in the frequency region that the bypass capacitors control is therefore proportional to L2+L1. To compute L2 (blue region), assuming that the field intensity generated between the planes due to a single via with diameter D falls off inversely with distance and is independent of height, use:

L2(spreading inductance) = (µ0/π)(H2 )ln(2S2/D)

With H2 in inches, the quantity µ0/π equals 10.16 nH.

The L1 computation (green region) divides into two parts; the part of the inductance due to the capacitor body and its pads, and the part due to the vias. The combination of body, surface-mounting pads, and via pads (assuming that the vias are jammed right up against the mounting pads) comprises a long, wide structure that resembles a transmission line. For example, a 0603 mounting structure is approximately 30 mils wide, 120 mils long (via center to via center), sitting at some height, H1, above the nearest solid reference plane. Given the characteristic impedance, Z0, for a structure with this width and height, and the time delay, T, corresponding to its length, you may approximate the inductive contribution due to the body and pads (ignoring fringing fields at the ends) as L1 (body)= Z0T. You can use any ordinary transmission-line calculator to approximate Z0 and T. Next, approximate the inductive contribution of the vias at the ends using the Biot-Savart law integrated over the blue region, assuming the vias represent tiny current elements. The result is:

L1 (vias) = (µ0/2π)(H12)(2/D – 1/S1)

Add the two contributions to find the total, L1. This approximation works only when S greatly exceeds D.

Figure 1 graphically depicts calculations for a 0603 layout, with the vias jammed up against the capacitor mounting pads. The figure shows the total inductance, L1, versus height. The assumed pad width is 30 mils, the total structure length (via center to via center) is 125 mils, and the via diameter is 12 mils. The x-marks show actual measured results. The value of L2 for this structure, assuming S2 =0.500 and H2 =0.005 is 0.22 nH. Both L1 and L2 vary strongly with height.

If you mount the capacitor on the reverse side of the board, you have to sum the various inductances L2A, L2B, and others (yellow regions), thus illustrating the disadvantage of backside mounting.

If you must use traces to connect the capacitor vias connect to the capacitor mounting pads, add the inductance of those traces to L1. At roughly 10 nH/in. for typical pc-board traces, the extra trace inductance quickly adds up. For example, 0.050-in. long traces at each end of a standard 0603 component adds around 1 nH to the completed layout inductance, substantially raising L1.