c Rising Problem

## Rising Problem

I've been working like a madman this Spring trying to complete our video studio. We don't have a lot of qualified help out here in the country, so last night I got "volunteered" to go up on a ladder and install the new phone lines. The new phones will support my occasional web seminars, and I'm working up to maybe doing some call-in talk shows over the web. We’ll let you know if that happens.

On the subject of movies, my production assistant Jennifer just finished editing a new-product-introduction movie for one of our clients. Now she’s beginning to think about my next project. Recently she hauled an old TV into the studio and asked if we could film a "kill your TV" spot, where I actually shoot the darn thing with a shotgun. I've heard that they explode nicely. Sounds kind of fun. I guess she thinks I need more fun lately…

I’ll be in Raleigh, NC teaching my seminars Oct. 31 - Nov. 2nd. Hope you can join me. I will not be wearing a costume for Halloween.

## Rising Problem

I’ve noticed a growing number of situations recently that involve what I call “phantom ringing”. That’s the sort of ringing that shows up in your simulator, but doesn’t really happen on the pcb.

A lot of things can induce phantom ringing. I have time today to look into only one: your choice of rising edge shape.

In a SPICE simulator, one of the simplest voltage waveforms to make is the piecewise linear (PWL) wave shape. The shape can be produced in only one line of code, with controllable rise time and amplitude. It usually comprises just three linear segments: a pre-cursor (flat), followed by a linear ramp (the edge), and finally a plateau (logic HIGH). For use with well-damped (i.e., non-resonating) circuits like transistor gates and other stuff on-chip, a PWL stimulation works well. In resonating systems it doesn’t.

Figure 1 compares three possible wave shapes: the PWL shape, a quadratic shape, and my personal favorite, the Gaussian shape. All three are adjusted to have the same 10-90% rise time. (The PWL shape has a 0-100% rise time of 8 ns. The 10-90% rise time works out to 80% of that amount, or 6.4 ns. In the other two shapes I set the 10-90% rise time to 6.4 ns.)

The Gaussian and quadratic shapes appear quite similar except at the ends. The Gaussian shape tapers less severely at the endpoints, never quite achieving 100, but, to put it in engineering terms, coming “close enough to kiss” within a short period.

To put this discussion in perspective, consider the circuit in Figure 2. The transmission line is only ½ ns long. That delay amounts to a very short fraction of the signal rise time. Such a short line delay might tempt you to assume the circuit will not ring. That would not be a bad assumption for a real digital system, but if you SIMULATE this circuit using a PWL edge (8 ns 0-100) you see something entirely unexpected.

Figure 3 plots the results of four experiments. First, to illustrate the nature of the resonance in Figure 2, I stimulated the circuit with a very fast step input. The response in that case (no edge shaping) rings mightily. In the frequency domain (Fig. 4), the resonant behavior creates a series of humps in the frequency response of the system output (SYSOUT). These humps appear at frequencies of 260 MHz, 1100 MHz, and so on. At 260 MHz the gain is almost +20 dB. Poorly terminated transmission lines always exhibit a series of such peaks. The positions of the peaks are related to the round-trip delay of the line with correction for the capacitive load at the end.

Whether or not the peaks cause noticeable ripples in your time-domain simulation depends on the frequency response of your rising edge. What you are supposed to do, if you want to eliminate the ripples, is stimulate the circuit with a highly filtered edge, one with practically no significant frequency content above some maximum cutoff. If the cutoff frequency of your stimulus lies BELOW the first resonance in your circuit, then you never see the effects of that resonance.

The same principle applies to digital logic. The approximate cutoff frequency (FKNEE) for physical digital logic equals one-half divided by the 10-90% rise or fall time of your driver. If the driver rise time is slow enough, then FKNEE is low enough, so that you don’t see the effects of circuit resonances. A slow rise time makes for good signal quality on an un-terminated transmission line.

For example, assuming a digital rise/fall time (10-90%) of 6.4 ns I expect a cutoff bandwidth of about 78 MHz. With such a low cutoff frequency, even a severe transmission-line resonance at 260 MHz should not sensibly affect the output waveform.

The PWL output in Figure 3, however, clearly shows ripples at 260 MHz. In this case the “rise time” measured 0-100% looks reasonable but the signal shape does not! The sharp corners of the piece-wise linear (PWL) edges kick the circuit with a splash of high-frequency energy on every transition. Those corners over-stimulate the resonant behavior at 260 MHz.

Figure 3 shows the system output results y(t) for all three edge types, PWL, quadratic, and linear. The PWL stimulus excites the worst behavior, quadratic is better, and Gaussian is best.

Each of the rising edge shapes acts as a filter. Figure 4 shows the frequency-response of each filter type. I’ve aligned the filter responses with the SYSOUT response, so you can imagine, for example, how much the filtering effect of the PWL edge (blue) might knock down the big peak in the unfiltered (fast-rising-edge) SYSOUT plot. At 260 MHz, the PWL edge provides not quite 20 dB of attenuation, yet the SYSOUT plot has an almost +20dB resonance at that point. Result: the resonant behavior creates lumps and bumps in the PWL output waveform (Fig. 3).

The quadratic edge provides better attenuation at 260 MHz, about 10 dB more than the PWL filter. As a result, 260 MHz ringing artifacts in the quadratic time-domain response are attenuated by 3x compared to the PWL edge.

Of the three simple choices discussed here, the Gaussian edge best represents actual digital logic. It has the best filtering at 260 MHz, more than 60 dB, and displays virtually no perceptible ringing in the time domain—just like the real circuit.

So, how do you make a Gaussian edge in SPICE? You can create a Gaussian edge with a mathematical spreadsheet (or EXCEL) and then read it into SPICE as a sampled waveform. The Gaussian edge is just the time-integral of a Gaussian bell-shaped pulse. Equations for the impulse response of a Gaussian filter (the bell-shaped pulse), the step-response (edge) and the frequency response associated with this function appear in Appendix B of my book, High-Speed Digital Design.

You can make quadratic edges by integrating ramps. To create a unit-height parabolic edge with 10-90% rise time T, first create a PWL response that looks like a triangle. Your PWL waveform should start at zero, proceed linearly up to amplitude (1.105573)/T at time (0.904508)T, and then return linearly back to zero at time (1.809017)T. Under this waveform lies a total area of one unit.

Pass the PWL triangle through an integrating circuit. The output will rise gracefully (quadratically) from zero to one.

If you don’t have a perfect integrator tool in your SPICE program, a simple R-C filter circuit followed by a voltage buffer can do the same job. Set the series resistor R to 1 Kohm and the shunt capacitor C to about 1 nF. Make sure the time constant RC is much, much larger than the length of the rising edge you plan to produce. Scale the amplitude of your triangle waveform by the factor RC. When you pass your triangle waveform through the R-C filter the buffered output will execute a beautiful quadratic rising edge with a 10-90% rise time equal to T.

Other filter structures, like Bessel filters, can also make reasonable approximations to real digital outputs.

Best Regards,
Dr. Howard Johnson