I am currently performing some signal integrity tests on a current design here in our lab. My question is: what is the correct method to measure the settling time of a digital waveform using the cursors provided with a DSO? I am using a Tektronix TDS 754 Digital Storage Oscilloscope.
Do I measure from the 10-percent point of the rising or falling edge to the point where the ringing is suppressed to 1-percent or less than the nominal amplitude?
Or. . .
Do I measure from the 90-percent point of the rising or falling edge to where the ringing is suppressed to less than 1-percent of the nominal signal amplitude?
Or. . .
Is either method acceptable?
I would appreciate your reply as my colleagues and I have differing opinions on the subject.
Thanks for your interest in High-Speed Digital Design.
Your question has a lot to do with how we define the "output delay" of a chip.
In general, we are interested in the total time taken for a digital signal arriving at one chip to go through that chip and propagate in a useful form to the next chip.
For this purpose we need to add together: (1) the input-to-output delay of the first chip, and (2) the propagation and settling time to the next chip.
For measuring item (2), the final settling value (1 percent or whatever) has to do with the voltage margin budget at the receiver. If you have very little crosstalk, for example, a residual ringing budget of 3 or 4 percent might not be unreasonable. I'm not going to quibble too much, though, with the general utility of the 1-percent figure that you are using.
More pertinent to your question is the issue of how the chip delay is defined. Some manufacturers will define chip delay as the time to a 10-percent point, or others to a 50-percent point, or still others to a 90-percent point on the output waveform. It is convenient to use the same convention for the starting position of your propagation-delay- and-settling-time measurement as that used by your chip manufacturer for the output delay. When the conventions are the same, you can just add chip-delay plus propagation- and-settling numbers directly. Otherwise, you need to add silly little correction factors to account for the different measurement conventions.
I feel I have made the situation worse for you, rather than better, with this answer, but hope that this note will have the beneficial effect of pointing you in the direction of also investigating precisely how output delay is specified on your chips.
Dr. Howard Johnson