In [Volume 1, Issue 4] of the newsletter, you discussed the technique of putting serial resistors on both ends of the transceiver pair. Can you expand that discussion on standard buses like the PCI bus or VME bus (incident-wave switching, p. 46 of the same Mindshare book on PCI system architecture), where each slot can drive the bus, not just the ends of the transmission line.
I also understand that the PCI bus utilize "reflected-wave switching" (p. 48 of the Mindshare book on PCI system architecture), that at each slot the bus is intentionally unterminated and cause a reflection that adds amplitude to the incident wave. Can you discuss these with us?
Thanks for your interest in High-Speed Digital Design.
The PCI bus is about 4 inches long, and may contain four devices in a standard configuration (although some people stretch it to eight).
The PCI bus operates a lot like a series-terminated line.
To derive the operational characteristics of the PCI bus, I like to start with a mental picture of an ordinary series-terminated transmission line. Give the driver a source impedance of 25 ohms, and make the line impedance also 25 ohms. It's kind of a low-impedance line, but it works the same as any other series-terminated configuration:
(1) When the driver transitions, we initially get a 1/2 sized wave on the line; (2) The 1/2 sized wave propagates to the far end of the line; (3) At the far end, a reflection of magnitude +1 occurs, sending a 1/2 sized wave back towards the driver; (4) When the reverse wave arrives at the driver, it is absorbed by the matching 25-ohm impedance of the driver; (5) At the far end, the receiver sees a 1/2 sized incoming wave plus a 1/2 sized returning wave, which adds up to one full-sized transition. After one round-trip, the entire line is stabilized.
OK, now what we'll do is divide the 25-line in half, lengthwise. Split it into two parallel lines, each having an impedance of 50 ohms.
The driver still has a 25-ohm output impedance, which then directly feeds both lines in parallel.
From a signaling perspective, nothing has changed. The initial wave is still half-sized. The far end still has the doubling effect, and sees a full- sized transition. Assuming the lines are of equal length, the returning waves arrive at the driver simultaneously, and are absorbed at the driver. After one round-trip, the entire system is stabilized.
The next step here is to layout the system differently. We'll keep the two 50-ohm, equal length lines, but instead of running them parallel, we will run one to the right, and the other to the left. The driver, with its 25-ohm source impedance, feeds the lines at their juncture. This is the PCI- bus configuration. If your driver is located exactly in the center of the PCI bus, and if its impedance equals 1/2 the line impedance, then it will launch and initial wave of 1/2 size, which propagates to the far ends of the bus. At the far ends, we get the doubling effect, and see full- sized signals. The 1/2-sized waves reflect off of the far ends, and head back towards the driver. The returning waves arrive at the driver simultaneously, and are absorbed at the driver.
The whole event takes only one round-trip time from the center of the bus to the ends and back. By that time everyone on the bus sees a full-sized signal, so we can clock the bus, and go on to the next bit. That's the theory.
Now let's look at the practical reality.
What about a driver is located at the end of the PCI bus. What impedance should it have? Well, this configuration looks like a standard series- terminated configuration for which the correct driver impedance should be 50 ohms, not 25 ohms. Yet we are expected to make cards that can plug into any slot. What impedance should we use, 50 or 25?
What about cards in other locations, neither in the middle nor at the ends? It turns out that for those cards there is no perfect solution, but it seems reasonable to pick an impedance somewhere between 25 and 50 ohms.
As you can see, this bus is going to be full of compromises.
Here are some other issues. Each transceiver connected to the bus loads down the bus, reducing its impedance. Therefore even if we match some "ideal" impedance, the driver won't always work properly when the bus is heavily (or lightly) loaded. How about chip tolerances? The chip manufacturers are trying to keep the bus really cheap, which means they want to integrate the driver output impedance control features inside the chips. No external resistors are supposed to be needed. That's a neat feature, but when it comes down to it you just cannot build a very accurate output impedance on a CMOS driver.
The final outcome of this mess of compromises is that the 2nd-reflected wave switching ideal is never achieved. What really happens is that we try to implement PCI drivers with some "reasonable" output impedance, not too high and not too low, so that they absorb a "lot" of the energy in the reflected signal at each passage. We plan to wait several round-trip times for the bus to settle. Then, to make sure the bus settles quickly, we make it REALLY SHORT. That constrains the round-trip time so that even if 3-4 roundtrips are required for settling time the bus still comes to stasis within about 10 ns.
That's it. The PCI bus in actual operation is not pretty, but it works.
Dr. Howard Johnson