The following simulations were generated by HyperLynx software. The driver in each case is a simple 3.3-V CMOS model, with 10-ohm output impedances in both HI and LOW states, 6-nH package inductance (BGA) and a 1-ns rise/fall time (10-90%).
The net topology shown on this page cannot be terminated satisfactorily. What I mean is, you can’t obtain crisp first incident waves at both endpoints, of full size, with no reflections, and still meet the demands of good circuit-design practice. You can satisfy any combination of three, but not all four, of the above requirements.
The basic problem with this topology is that all three branches are long compared to the length of a rising edge. In other words, the signal delay on each branch (about 1 ns) is comparable to the risetime (also 1 ns). Such a net, if left unteriminated, will display full transmission line characteristics, with lots of overshoot and ringing.
Begin by looking at the performance of the unadorned net. All traces are 50-ohm configurations. There are no terminations. The charts show the voltage waveforms at the driver (A) and the receiver (C, D) locations. Both the receiver waveforms are the same. A step response test is shown on the left, and a 66-MHz clock waveform on the right. In each case, the driver waveform responds first (the line delay is about 2 ns).
The system rings prodigeously, and look at that overshoot! The signal flies up to over four volts. That's too high, we risk damaging the 3.3-V receivers. We've got to do something. Let's try a slower driver.
When a system rings, that usually inidicates that the system delay is too long compared to the driver rise or fall time. It's the ratio of delay to rise or fall time that matters. If you can reduce that ratio, things get better.
A slower driver should improve the ratio of line delay to risetime. I tried a variety of different speeds until I found something that damped the step-response oscillations. A speed of 15-ns seems about right.
As the step response waveform shows, the 15-ns driver cures our overshoot and ringing problem, but, unfortunately, this approach completely blows it on the first criteria: a nice, crisp first incident wave. Look at the 66-MHz clock response. It's way too sluggish. This won't work.
If the problem is damping, let's add terminations at every endpoint. Add a source termination of 50-ohm at the driver, plus end-terminations of 50-ohms at each receiver.
The signal quality looks excellent, but the both-ends termination approach cuts down the signal amplitude to only 1/3 of normal size. With specialized receivers, this architecture can work wonders. With ordinary single-ended logic receivers, the diminutive received signal is useless.
A partial termination, even if it’s not the correct value, always helps calm reflections. I'll try that next.
In this example, the driver connects directly to the line (no resistor). Each receiver is equipped with a 100-ohm split termination (200 ohms to ground and 200 ohms to Vcc). I selected 100-ohm terminations in this example because this driver cannot drive two 50-ohm loads at once and still meet its VOH and VOL requirements.
The first incident wave definitely appears larger, but reflections trapped between the low-impedance driver at A and the mismatch at junction B cause the received signal to overshoot, crest, and rattle about. Also, the first edge at startup is not quite making it up to VOH.
A Sneaky Trick
If we are willing to use a sneaky trick, we can satisfy the first three conditions. The trick is to implement segment A-B as a 50-ohm line, while implementing segments B-C and B-D as 100-ohm lines (it takes really skinny microstrips to get this to work, but it’s possible). When the signal from A hits junction B, it sees two 100-ohm loads in parallel, which is a good match for the 50-ohm segment A-B. No reflections result. Two 100-ohm end-terminations, one at position C and another at position D, will now perfectly terminate the whole net.
The little blip 4 ns into the step response is caused by the parasitic capacitances of the receivers, which are each set to 3 pF for this simulation.
Is the sneaky trick a good practice? That depends on your company’s internal design procedures. Most companies do not have a good way to document, track, and enforce tricky high-speed design rules. For example, if you write a little thesis on your schematic about some high-speed design trick you’ve used it’s unlikely that the layout person will ever see it. It’s not their job to read your schematic. It’s their job to hook up the net list, with the part footprints in their database, and the standard design rules enforced in their shop at the time of layout. Even if you get it right the first time, when the Tee layout is revised, as part of a future product upgrade, if you’re not there, the design is likely to get screwed up.
If you throw the Tee overboard the situation improves. For example, a pair of low-skew drivers at (A), with independent, point-to-point links to each load, would eliminate all the tricky constraints.
Sneaky idea with source termination
If you convert the sneaky topology back into a source-terminated configuration, and if the line lengths are identical and the loads perfectly symmtric, even the tiny blip 4 ns into the response goes away.
This time trace A-B is 50 ohms, each trace B-C and B-D are 100 ohms. There is a single 40-ohm series termination placed at point A (NOTE: the 40-ohm resistor plus the 10-ohm output impedance of gate equals the 50-ohm impedance of line). Segments B-C and B-D are the same length.
There appears to be some magic in the sneaky idea of impedance modulation. Got any ideas what could go wrong with this scenario?
Sensitivity to imbalanced load
Consider what happens if the loads are not symmetric. Use the same setup as before, with a 50-ohm source termination, but modify the load capacitances at the receivers. Set one receiver to 3 pf, and the other to 1 pf. That's only a 2-pf difference, but look what it does to the signals. (Only one of the two received signals is shown.)
This system seems pretty sensitive to delay, isn’t it! An end-terminated system might be less sensitive to delay balance, because it terminates two of the three endpoints. That prevents almost every possible mode of signal rattling.
In the series-terminated case, signals can bounce from (C) to (D) and back to (C) unimpeded by any termination. That's the effect you see in this figure.
End termination is less sensitive
The end-terminated case is not quite so sensitive loading in the end segments. Let’s keep the unbalanced capacitive loads, but go back to a 100-ohm termination at each endpoint, and a direct hook-up (no resistor) at the driver.