Raymond Bullilngton writes:
I am designing a piece of equipment to interface to a digital tape recorder de-signed by another company. This recorder uses a differential ECL interface, and the user's manual recommends terminating the clock lines slightly differently from the data lines. Each clock line has a split terminator, 160 Ω to -5.2V and 100 Ω to ground, and the data signals simply have a single 120-Ω resistor between the ± pair. Because these two methods are Thevenin equivalents, why does the user's manual recommend different termination schemes? As far as I can tell, the transmitters and receivers for the clock and data lines are electrically equivalent, and all signals have 39-Ω pulldown resistors to -5.2V at the transmitter, to prop-erly bias their emitter-follower outputs. I have contacted the company that de-signed the circuit, but the original designers are unavailable. Does one termination scheme have any advantage over the other?
Engineers often have a difficult time figuring out why something was done. Sometimes there is no reason, sometimes there is a multitude of reasons, and sometimes (as is common in the standards world) everyone wants it done the same way but all for different reasons.
Anyway, differences do exist between the termination schemes you described. The single-resistor scheme (a single 120-Ω resistor across the two lines) terminates all differential-mode signals into an impedance of 120 Ω but provides no termination for common-mode signals.
Your four-resistor scheme (independent terminations for each line) terminates all differential signals and all common-mode signals. The difference between these two styles matters only if a common-mode signal is present. And where might that signal come from? It comes from skew in the clock driver.
Consider the single-resistor termination shown in Figure 1. Say that the signal, x(t), arrives first on trace A, and then, after a tiny skew interval, the opposite signal –x(t–Δt) arrives on trace B. During the tiny skew interval Δt a single 120-Ω resistor, R1, would create two tiny artifacts. First, the initial rising edge on A would just shoot around the resistor onto trace B, creating a little blob of crosstalk, Tx(t), on wire B, where T represents the magnitude of the "transmission coefficient" governing what fraction of signal x(t) makes it around to the other wire. At the same time, you would get a little reflection, Rx(t), back onto A, where R represents the magnitude of the signal reflected back onto wire A.
After time Δt, the opposite edge –x(t–Δt) arrives on B. Then you get another set of crossed and reflected signals but with opposite polarities. The second set of artifacts partially cancels the first, with the degree of cancellation depending on the exact temporal alignment of the two signals. The crosstalk and reflections perfectly cancel only when the signals on A and B arrive perfectly synchronously.
In this example, both coefficients T and R equal ½, so you may reduce the equations to a single expression for the residual common-mode signal, z, induced on either trace by the single-resistor end-terminator: z(t)=½(x(t)–x(t–Δt)). If the skew is less than the signal rise or fall time, t10-90%, and you define the signal step height as Δt, the amplitude of the common-mode noise pulse generated on each signal transition is:
Common-mode pulse amplitude = ½ΔV(Δt/t10-90%)
Once created, the common-mode noise pulse returns to the driver where it encounters a low-impedance source, generating a big reflection. The reflected noise then proceeds to the receiver where it encounters the single-resistor termination. Because the common-mode noise pulse presents the same voltage on both traces, the single-resistor terminator draws zero current, acting as an open circuit and generating another big reflection. The common-mode artifacts happily bounce back and forth between driver and receiver for a long time. Terrible things can happen to these common-mode artifacts if your trace delay equals one-quarter of the clock period. In that case, the little common-mode artifacts build and superimpose, cycle after cycle, magnifying your common-mode signal-input-range problems at the receiver and also magnifying the radiated emissions. Your four-resistor termination independently terminates both lines, so neither the common-mode range nor the radiation is magnified. As long as you are working with a 50-percent duty-cycle clock signal, consider using the independent termination in Figure 1. It terminates both differential and common-mode signals but requires only two resistors. The capacitor need be only large enough to hold its charge steady during the brief interval, Δt.