Have you noticed what's happening in the world of clock specifications lately? It used to be that the only things that mattered in a clock specification were the frequency and the duty cycle. Between these two specifications, vendors were really just setting limits on the minimum time high and the minimum time low each period. A few complications arose with the advent of DRAM technology, like the need for maximum bounds on the clock period, but that was about it.Recently the whole clock scenario has undergone massive change, due mostly to the widespread use of PLL-based clock recover schemes used in serial data communications equipment, PLL-based clock multipliers, and PLL-based clock regenerators. The basic premise of a PLL is that it carefully adjusts its own clock, called the local oscillator, to bring it into precise alignment with some external signal, usually called the reference clock.
The PLL concept was originally developed for use in radio, and later adapted for use in serial data communications. In the serial data communications application, the reference clock is often embedded, sometimes in very subtle ways, in a stream of data bits. It is the job of the PLL in the clock recovery subsystem to align its local oscillator with the reference clock information embedded in the data stream. Once properly aligned, the local oscillator can be used to clock bits out of the data stream, sampling each data baud right in the center, at the point of maximum noise immunity.
In this application, any imperfections in the transmit clock used to construct the data stream may compromise the ability of the PLL to properly align its local oscillator. Imperfections in the transmit clock are sometimes classified as frequency offsets, wander, and jitter.
The term frequency offset refers to any long-term deviation between the actual transmitted clock frequency and the ideal. For example, crystal-controlled transmission systems can be expected to attain frequency offsets as low as a few hundred parts per million. This sort of specification is measured with a frequency counter, averaging all clock pulses over a period of perhaps many seconds.
A PLL-based clock recovery subsystem is designed to accurately lock-in to any reference signal within the permitted frequency offsets. The frequency offset specification often has more to do with whether a PLL will lock-in than with the quality of clock recovery, once lock-in has occurred.
Clock wander refers to the tendency of a clock reference to exhibit short-term frequency variations. A PLL is designed to track the short-term wander, provided that it does not slew too fast or wander too far afield. The permitted amount of wander, the rate of which a signal may wander up and down across the permitted frequency rate, and the slew rate of the wander are often key components of a good wander specification.
Jitter refers to the fastest variations in clock frequency. It comprises those variations too fast to expect the PLL to track, and therefore jitter always directly affects the accuracy of the timing relation between the reference clock and the local oscillator. In a data communications application, excessive jitter causes bit errors.
OK, so clock purity is important in data communications applications, we all knew that; but what does clock purity have to do with plain old digital design? Plenty, as we will see, because the same PLL-based clock recovery technology is being widely used to generate multi-hundred megaHertz, very low-skew processor clocks in the latest generation of clock-generator chips from AMCC, Chrontel, PLX, Quality Semiconductor, Triquint, and many others.
These new clock generators are flexible, fast, and packed with features. Most incorporate three basic ideas: a reference clock, a PLL clock multiplication circuit, and a means of maintaining very low skew among multiple clock outputs.
In a typical clock multiplier application, the reference clock is often sourced at about 10 MHz from a traditional crystal oscillator. 10 MHz is a very comfortable range for crystals, and it's a good bet you already have one in your system.
To multiply the clock, it is run into a PLL-based clock multiplication circuit. In a multiply-by-ten circuit, for example, the PLL aligns every tenth edge of the local oscillator to the reference clock, thus generating a 100-MHz output. PLL technology can also be used to create zero-delay clock buffers, automatically adaptive skew correction circuits, and other neat features. The combination of PLL, output drivers, and skew correction circuitry is fabricated as a single chip.
What can go wrong? Plenty. Suppose we are feeding rotten power to the crystal source (maybe it has 100-KHz switching noise on it from the power system). If the crystal output violates the offset, wander, or jitter tolerance of the PLL circuit, the 100-MHz output goes nuts. It may fail to lock, drifting to one end or the other of its range, it may flagellate up and down, or, depending on the PLL architecture, it may detect an absence-of-lock condition and just shut off.
What if the clock multiplier is built inside your processor (like with an Intel Pentium processor)? Then the quality of the incoming clock has everything to do with the quality of the resulting system.
If you are using a clock multiplier, or a PLL-based clock regenerator, make sure to comply with the specifications for offset, wander, and jitter on the reference clock input. If you have the specifications, test them; if you don't have the specifications, get them, and if your vendor won't fork them over, think carefully about the consequences before you move ahead with your system design.