## Crosstalk - Via to Trace

Welcome to the New Year. When you receive this letter I will be at home, busily preparing new material for my public courses in Boston March 7-11, and then Austin, TX the week of April 11. The Advanced High-Speed Signal Propagation course includes a new section on AC coupling, a better focus, with more examples, less math and oodles of new animations.

## Crosstalk - Via to Trace

Frank Amato at Connexant writes:

We are having a debate about the minimum separation between a differential analog pair and a digital via on the same PCB. Can you show the equations to calculate the crosstalk between a multi-layer via and a differential pair of traces and the corresponding explanation?

Thanks for your interest in High-Speed Digital Design.

Regarding your inquiry, there are two types of electrical coupling: inductive (magnetic fields) and capacitive (electric-fields).

First let's deal with magnetic effects. The via has a vertical orientation and a trace horizontal orientation. Since these two objects carry current in perpendicular directions, the magnetic interactions null to zero. The same thing happens in the case of two traces crossing at right angles—no magnetic interaction.

That leaves us with just electric-field (capacitive) effects. The mutual capacitance from the via barrel to the nearest trace will create a certain amount of unavoidable crosstalk that will not be cancelled by the antipodal trace of your differential pair unless both traces pass at equal distances from the via (i.e., the via "splits" the two traces symmetrically). Thus we have two questions:

1. How big is the mutual capacitance, and
2. Is it a good idea to "split" the analog trace with the via?

My answer to the second question is a firm no. While the splitting idea appeals to me intellectually, it should not be attempted, as even the slightest imperfection in symmetry will result in noticeable differential noise coupling. In addition, the splitting approach encourages common-mode coupling to both traces that, while it might not affect a "good" differential receiver, does indeed couple digital currents directly into the analog region where you do not want them. So how about the first question? The answer to that requires some lab work...

### A day in the lab

Today I set up the following experiment involving two solid reference planes separated by distance H.

I placed one signal via in the center of the planes. It penetrates completely through the layer stack. All interior pads are stripped from this via.

I placed one stripline trace embedded precisely halfway between the planes. The trace extends well beyond the via in both directions.

The experiment uses an HP 4271B LCR meter to measure the mutual capacitance between via and trace. Here are the particulars:

• The ratio of via diameter to H is 1:3 (e.g., 21-mil spacing with 7-mil hole)
• The ratio of trace width to H is 1:4 (typical for 100-ohm differential striplines)
• The ratio of trace height to H is 1:2 (it's in the middle).
• The spacing S from trace to via is variable.
• Pads are stripped from all unused layers on the via.
• The trace is 8H long, centered at the via location. I verified that the incremental contribution of trace length beyond this amount is less than my experimental error. The experimental error from all sources I estimate at about ten percent.

The system under test uses an air dielectric so I can physically move the trace while observing changes in mutual capacitance. The trace is suspended on dielectric supports of negligible size. The system under test is made large enough so I can get my hands (and a caliper) inside it to make the adjustments.

You can easily translate my measurements made using a large-scale model with an air dielectric into your world of practical applications involving tiny dimensions and typical pcb dielectric materials. To make the translation, you need two rules of scaling.

1. Physically scaling the entire model (height, width, length, separation, everything) by a scale factor k changes the measured capacitance by the same scale factor k. This is an exact result from Maxwell's equations.
2. Filling the interplane cavity with a material having a dielectric constant Er changes the capacitance by a factor of Er. This is also an exact result.

I present my results assuming a standard height H equal to one inch and no dielectric filling. If, for example, you use a height H' equal to 0.020 in. with Er=4.1, scale my spacing values by the factor 0.020 and my capacitance values by the factor 0.020*4.1 to obtain a new table of results good for your application.

Table 1—Measured values of via-to-trace mutual capacitance

Spacing Mutual capacitance (pF)
0.238 0.203
0.412 0.119
0.854 0.031
1.667 0.005

NOTE: These values assume H=1.00 in. and Er=1.00 (air). The spacing S appears in inches. Your values of H and Er will differ.

The mid-level position adopted for the stripline trace in my experiment is the least favorable position for crosstalk. Traces located nearer one plane or the other will experience less mutual capacitance. Adding pads to the via, or enlarging the via barrel diameter, will increase the mutual capacitance.

The impact of via-to-trace mutual capacitance is this: a rising edge of height Vs (volts) and risetime Tr (s), acting through a mutual capacitance of Cm (F) onto a trace having odd-mode impedance Z0 (ohm) will produce a crosstalk pulse having an amplitude A approximately given by: Example:

• Height H = 0.020
• Spacing S = 0.033 in.
• Er = 4.1

The ratio S/H equals 5/3, which corresponds to the last row of the table. Scale the capacitance in that row H=0.020 and Er=4.1 to produce Cm=0.005*0.020*4.1=0.00041 pF.

Assume:

• Vs = 1.0 volt
• Zodd = 50 ohms
• Tr = 100 ps Eighty dB is plenty for some applications, not enough for others. Figure 1—Data from the crosstalk table, reduced using  according to the assumptions given above.