## Bidirectional Alternatives

Ron Shideler writes:

I would like to comment on your response in your newsletter on Bi-Directional Terminations and ask you a follow up question. I understand what you are saying in your comments but this only solves a particular case of a point to point link where you basically have two sources and 2 end points with devices placed only at the end points.

With series termination the signal on the transmission line won't reach a valid logic level until it hits the end points. The valid end point will depend on whether A or F is driving.

I see the situation like this:

A--RR--B--------------------------------X--RR--Y

**Where:**

- A, B, X and Y are I/O ports connected to a common bus,
- B and X are receive-only devices,
- RR is a series terminating resistor (in 2 places),
- the line between B and X is really long,
- and where all other lines are short.

To me this means that A could only broadcast to X or Y and that Y could only broadcast to A or B. I don't see how you could get it so that each transceiver could broadcast to each of the receivers B and X.

In a multiple processor design there is typically more than 1 source (2 processors) and multiple end points (CPU core). If we assume the CPU core is distributed between the two processors.

This makes the situation even worse:

A--RR----B----C----D----... ...-----X---Y---RR--Z

There is no way to put a CPU core (SRAM, DRAM, FLASH, etc) next to each other so there would have to be space between the individual CPU core components. All the receiving devices would have to be spread across the line since there is physically no space to lump them together. I don't see how series termination will allow a valid Vih, Vil at each device in the chain.

Is there some other termination method besides the diodes for this type of transmission line?

Thanks for your interest in high-speed digital design.

The setup in my previous article was for two transceivers, A and Y:

A--RR--------------------------------------RR--Y

**Where:**

- A, and Y are I/O ports connected to a common bus,
- RR is a series termintating resistor (in 2 places),
- the line between RR and RR is really long, and
- where all other lines are short.

You are correct that this bi-directional setup only guarantees first incident wave switching to the endpoint located opposite the driver. Any other receiver you daisy-chain along the way will get a 1/2-sized step, followed later by the another 1/2- step which will bring it up to full voltage. This action may not sound so great at first, but AT LEAST it does guarantee that the line will stabilize within one round-trip time.

If you intend to put together a multi-drop bus (without end terminations) I should like to point out two ideas which may help.

(IDEA 1) A receiver located right next to the first transceiver (BEFORE the series-terminating resistor) is in a privileged position. It gets a full-sized signal immediately. Here's the architecture:

A--B--RR----------------------------------RR--X--Y

I've got a clump of transceivers located very close together at one end (A and B). They are connected together. Then I have the first series-terminating resistor RR. Then comes the long transmission line (with no intervening loads). At the end of the line is a second series terminator RR, followed by a clump of multiple loads all tied together at the far end (X and Y).

This is a rather specialized topology, and won't always suit your needs, but if you keep A, B and the first RR within 1/10 of a risetime, and the same for X, Y and the other RR, it does work exceptionally well. You may place any number of loads at either end.

(IDEA 2) You could try the PCI v2.1 bus architecture. The PCI v2.1 bus is about 4 inches long, and may contain four devices in a standard configuration (although some people stretch it to eight).

I've seen a lot of confusing explanations about how the PCI concept works, and I'd now like to throw my explanation out into the fray, with a few diagrams to bolster my explanation in PCI Bus -- v2.1. I hope this expanded description helps you understand the concept behind this style of bus. (By the way it's not a new concept, but it is well- applied to the PCI problem).

The PCI bus operates a lot like a series-terminated line.

To derive the operational characteristics of the PCI bus, I like to start with a mental picture of an ordinary series-terminated transmission line (fig. 2). Give the driver a source impedance of 25 ohms, and make the line impedance also 25 ohms. It's kind of a low-impedance line, but it works the same as any other series-terminated configuration: (1) When the driver transitions, we initially get a 1/2 sized wave on the line; (2) The 1/2 sized wave propagates to the far end of the line; (3) At the far end, a reflection of magnitude +1 occurs, sending a 1/2 sized wave back towards the driver; (4) When the reverse wave arrives at the driver, it is absorbed by the matching 25-ohm impedance of the driver; (5) At the far end the two waves superimpose. The receiver sees a 1/2 sized incoming wave, plus a 1/2 sized returning wave, which adds up to one full-sized transition.

A--R25-------------------------------------- (Z0=25)

OK, now what we'll do is divide the 25-line in half, lengthwise. Split it into two parallel lines, each having an impedance of 50 ohms.

/----------------------------------- (Z0=50) A--R25-| \----------------------------------- (Z0=50)

The driver still has a 25-ohm output impedance, and directly feeds both 50-ohm lines in parallel.

From a signaling perspective, nothing has changed. The initial wave is still half-sized. The far end still has the doubling effect, and sees a full- sized transition. Assuming the lines are of equal length, the returning waves arrive at the driver simultaneously, and are absorbed at the driver. All we have done is split half the current into each 50- ohm transmission line.

The next step here is to re-layout the system. We'll keep the two 50-ohm, equal length lines, but instead of running them parallel, we will run one to the right, and the other to the left. This is the PCI-bus configuration. If your driver A is located precisely in the center of the PCI bus, and if its impedance equals 1/2 the line impedance, then it will launch and initial wave of 1/2 size, which propagates to the far ends of the bus. At the far ends, we get the doubling effect. The returning waves arrive at the driver simultaneously, and are absorbed at the driver.

-------------------------------------------- (Z0=50) | R25 | A

The whole event takes only one round-trip time from the center of the bus to the ends and back. By that time everyone on the bus sees a full-sized signal, we can clock the bus, and go on to the next bit. That's the theory.

Now let's look at the practical reality.

What about a driver B located at the end of the PCI bus (figure 5). What impedance should it have? Well, when XB drives it looks like a standard series- terminated configuration for which the correct driver impedance should be 50 ohms, not 25 ohms. Yet we are expected to make cards that can plug into any slot. What impedance should we use, 50 or 25? And how about cards in other locations, neither in the middle nor at the ends? It turns out that for those cards there is no perfect solution, but it seems reasonable to pick an impedance somewhere between 25 and 50 ohms.

B--R??-------------------------------------- (Z0=50) | R25 | A

As you can see, this bus isn't going to be perfect, but it will do one very important thing: it limits the number of round-trip times you have to wait before the bus stabilizes. This is dramatically better than having no terminator at all.

Here are some other issues to keep in mind when using the PCI concept. Each transceiver connected to the bus loads down the bus, reducing its impedance. Therefore even if we match some "ideal" impedance, the driver won't always work properly when the bus is heavily (or lightly) loaded. The best driver output impedance is about 70% of the "loaded" impedance of the bus structure.

How about chip tolerances? Everybody wants to keep bus designs really cheap, which means they want to integrate the driver output impedance control features inside the chips. No external resistors are supposed to be needed. That's a neat feature, but when it comes down to it you just cannot build a very accurate output impedance on a CMOS driver. You have to have a tolerance band (perhaps as wide as a 3:1 ratio). This uncertainty in the output impedance adds to the number of round-trip times you have to wait.

The final outcome of this mass of compromises is that the 2nd-reflected wave switching ideal is never achieved. What really happens is that we try to implement PCI drivers with some "reasonable" output impedance, not too high and not too low, so that they absorb a "lot" of the energy in the reflected signal at each passage. Then, to make sure the bus settles quickly, we make it REALLY SHORT. That constrains the round-trip time so that even if 3-4 roundtrips are required for settling time the bus still comes to stasis within about 10 ns.

That's it. The PCI v2.1 concept in actual operation is not pretty, but it works.

Best Regards,

Dr. Howard Johnson