J.J. Leu writes:
I have a question about overshoot and undershoot. As we know, if source impedance of a driver mismatch trace impedance, overshoot and undershoot will exist in a receiver end, assume that source impedance is smaller than trace impedance, and the driver and receiver devices are CMOS type. What is the influence of overshoot and undershoot in the receiver end? That is, will overshoot and undershoot impact receiver end, damage it or cause excessive recovery time? Is there a maximum overshoot voltage or a maximum undershoot voltage for 3.3V or 5V devices? Does the maximum voltage depend on chip vendors?
Thanks for your interest in High-Speed Digital Design.
Overshoot can in severe cases cause CMOS latch-up and destruction of the receiver. Many CMOS receivers include built-in protection diodes on every input to preclude this possibility. Some don't. In particular, watch out for 3.3-V parts with 5-V "tolerant" inputs. There are often no protection diodes to Vcc on these parts.
When the protection diodes are present, overshoot, if it over-stresses the protection diodes, can cause aluminum migration in the diode contacts and eventual failure of the diodes. Nobody seems to know (or will say) under what general conditions this will happen. The maximum voltage (and maximum current) ratings for inputs remain peculiar to each vendor.
On another subject, milder amounts of overshoot, and the consequent ring-back will affect your timing margin. Basically, you have to wait for the ringing to settle down before it's safe to sample the received signal. This is the most common problem caused by overshoot.
Dr. Howard Johnson