Thank you for the interesting article on power plane resonance in EDN, 9/1/98.
My interest was attracted because of the extensive research and theorizing that I have done together with Richard Ellison (recently retired from Raytheon/E-Systems) on this very topic. Our investigations began a couple of years ago with the necessity of bypassing an extremely power hungry ECL ASIC mounted on a VME-3U-sized card. At 13 Watts and 44, 350ps ECL output pairs, a formidable task.
First, we built a special 4-layer circuit board for our study of power planes and bypassing. Try science first, we reasoned, then use the results to aid our simulation efforts...ya, sure, ya betcha! The board has two equal sized power/ground plane sandwiches and bypassing capacitor arrays with equal number of components. One plane is 4 x 6 inches the other about 5-9/16ths inches in diameter. Both plane sandwiches are 24 square inches in extent. The power/ground sandwich is a 4 mil 1-over-1 oz. Getek core. Equal thicknesses of Getek prepreg were used on both sides to build the stackup to nominal thickness of 60 mils. One ounce Cu. was electroplated on the outer surfaces for the component mountings and to form the thru-hole plating. Board material was Getek because its characteristics are similar to Polyimid but cheaper to fabricate. (Remember, the project cost was on overhead)!
Both planes have 77 positions for 0805-sized bypass capacitors. A 200pF (design value) test capacitor was also built in the board as well as calibration load positions for a network analyzer (an open, a short, a 50-Ohm resistor and a sample capacitor on the same pattern as used on the planes).
Capacitance of the rectangular plane is 6690pF and the circular plane is 6550pF. Measurements on the HP 8753D network analyzer to 6GHz indicated no resonances below about 1.25GHz. The planes look like very good capacitances, with reactances below 2 Ohms. The resonances we measured appear to be partially the result of the connectors used (SMB) and their attachments. We plan to retest with SMA connectors soon and think this will confirm our suspicions plus providing evidence of the connector's performance, a bonus. We have also learned quite a bit about bypass component mounting and connection methods to the planes. One via per end is not enough!
Our biggest difficulty in measurement is the extremely low impedance of the planes. We have found this a significant impediment to making measurements with anything like good resolution. This would take an instrument with a characteristic impedance of say 2 X Zo. Every piece of test equipment we have used for measurement has a 50-Ohm characteristic impedance. They are operating into what is, to them, a virtual short-circuit, We had hoped to be able to excite the planes at there center with a pulse of variable risetime and observe it as it propagated out to the edge. We, too, hoped to see that elusive and largely hypothetical reflection! The method in our madness in making the 2 planes in the shapes we did was to actually observe the propagation delay difference of the phantom reflections returning from the plane's edges. So far we have found the planes vault-like in their refusal to give back that pulse...anywhere! They are a most effective energy sink! The tiny outbound signals we could observe near the feedpoint had very (!) slow risetimes. Our TDR's risetime is under 25ps but it simply vanished within 1cm from the feedpoint. The TDR indicated a very good short indeed. Its risetime (yes, we could see a little rising signal level, but precious little) at the feed point was extremely slow...too long to measure. (We even tried a pulse-risetime measurement to determine the capacitance to little avail).
Next, we are devising a tester to jolt the planes with 10V to 12V sub-nanosecond pulses, sort of a monster TDR with characteristic Z of 1 to 10-Ohms, whatever we can perfect. Shades of Tesla, but more later on this saga...
We have hopes of simulating the planes to correlate with our measurements, if we can get some measured data... It has proved to us that all of the theorizing in the world comes a cropper against reality in situations like this. We know that the actual system built using this plane sandwich worked beautifully. Those sub-350ps edges from 44 pairs of differential ECL outputs were beautiful...no phantom reflections from the edges...even on the clock. (This little board consumed over 13 Watts and had only one IC on it)!
We may be cowed but we are not defeated. We are marshalling our forces for another frontal attack on these fortress planes. And this time we shall breach their walls and lay their secrets bare! Or we may give the board the smoke-test...
Thanks for your interest in High-Speed Digital Design, and for the interesting report on your measurement experiences. It's always nice to hear from people who are making real measurements.
When you say you are using a TDR instrument, I assume you mean you are doing a single-point measurement, where you inject a signal at point A, and then measure the reflections generated by the load at A as seen at the source end of the TDR step generator. At the source end, you must subtract the outgoing source waveform in order to compute the returning reflection. The precision of this measurement is affected by the accuracy with which you can subtract the outgoing source waveform. That accuracy forms a lower bound on the size of the smallest signal you will be able to observe. If the impedance of the planes is really low, you won't see anything.
Regarding your monster-TDR, even if you achieve an output impedance of 1 ohm, the plane impedance will be still much lower than that. Your TDR will act like a current source (which is pretty much what the logic gates will do). That's also how the 50- ohm source works. It looks like a current source, and you will have the same measurement problems with a TDR setup (i.e.), that the power/ground impedance is not sufficiently different from a true short to ground to give you a meaningful result within the noise measurement limits of your TDR instrument.
Rather than using a TDR measurement, I'd like to suggest that you do something more like a network analyzer setup (but in the time domain, not the frequency domain).
Apply your fast current step (from the 50-ohm source) to the board, and then monitor the voltage across Vcc and Gnd.
I'd put the source cable on one side of the board, and the pickup cable on the other side. Keep them on opposite sides so the direct coupling from one cable to the other won't corrupt your measurements.
The ratio of voltage out to current in is the impedance number you seek. The advantage of this method is that now you can just turn up the gain on the pickup until you see a measurable result. The Fourier transform of the step response should correspond exactly with (1/S) times the network analyzer plot you got from your HP 8753D network analyzer.
Another suggestion is that you inject a short pulse, as opposed to a step. The step waveform will show you a long, R-C buildup corresponding to the overall capacitance of your planes, in addition to the small, high-frequency signals you wish to observe. If you use a short pulse, most of the long R-C buildup will disappear, leaving only the signal you seek.
Let us know how this experiment turns out.
Dr. Howard Johnson