I attended your tutorial in San Francisco. I had an idea that you might consider for your inductance demo.
You made a big loop of wire, then a big loop of thin wire, then a ceramic disk capacitor with long legs.
You might try to make the loop and the loop with thick wire have the same dimensions as the capacitor with long legs. The measured inductance values would come out the same! Obvious once you know it, but not before you know it.
I do a lot of 6 layer boards, and have switched over to your suggested 6-layer stack, even for prototypes. I changed one board at fab after getting back to work from your second day of talk.
Here is an idea, and I wonder if you think it is good enough that you might recommend it.
On the layer below the ground plane, call it INT1, there will be places where there are signals. However, there will be large areas, perhaps mostly around the outside of the board, where there are no signals. I could put islands of etch there, and connect it to VDD with many vias. On the inner layer near the VDD plane, there are unused areas, and again I could make areas that are connected to GND with a swiss-cheese of vias.
Your stackup has maybe 50 mills between the VDD and Ground plane, but it has good signal crosstalk characteristics because of the 5-mill signal-to-plane spacing on all layers.
This use of the outside of the inner layers (and perhaps the outer layers too) might double the area that VDD is near GND, and the layer separation would be 5 mills instead of 50. This might make a significant increase in the VDD-GND capacitance, maybe 2X or 5X. It would not add any layers, so would not cost much. The board would be a better conductor of heat too.
I may try this. Do you offhand know what the knee frequency of a PCI system is? I am in the middle of several of those now.
I have so many ideas from your talk. I am telling everyone I know that they should take it.
Thanks for your interest in High-Speed Digital Design, and for your ideas about the demo.
Regarding your very interesting suggestion about the ground/power planes, it looks to me like it would really work. Your scheme multiplies the effective capacitance per square inch by a factor of 40 (if you put fill on all four signal layers, 5-mil above the nearest reference plane, and assuming an initial interplane spacing of 50 mils). That means that one a square board, a rim of material 1% of the board width, all the way around the edge, would provide 1.6 times as much capacitance as the natural interplane spacing. That will help hold down the Vcc-Gnd impedance at very high frequencies.
Note that, because your new capacitance is present only at the edges of the board, it is not immediately accessible to chips in the center of the board. At very high speeds, the bypass capacitance needs to be within less than 1/10 of a rising-edge-length in order to function effectively. On a small board, where interplane capacitance is naturally very low in the first place, your scheme would be most effective.
Dr. Howard Johnson