We are trying to understand how high speed return signals travel on a 4 layer pc board. When a topside trace is looked at on a TDR machine, we notice that the impedance measures the same if we inject the tdr signal between top side trace and ground, or the top side trace and the voltage plane. So it appears the return signal is following the path of least inductance on the power plane next to the top layer trace. What puzzles me is how the trace couples back to the ground plane below it.
Thanks for your interest in High-Speed Digital Design.
When you report that you inject the signal between the signal trace and the ground plane, I infer the following (please let me know if I make the wrong assumptions): Your signal stack looks like this:
S1 - P - G - S4
- S1 and S4 are trace layers, and
- P is the power plane, and
- G is the ground plane.
In this system there are two primary paths that can convey current from one plane to the other. The paths are (a) through the natural interplane capacitance, and (b) through bypass capacitors. How much current flows each way depends on the frequencies involved (or, equivalently, the scales of time), and the relative impedances of the two paths.
In order to determine the exact path, we need to know more about the structure of the board.
For example, you haven't told me the spacing between the power and ground planes. Some people spread them widely, in order to gain better crosstalk control between the traces on each layer. That would put the P-G spacing at about 0.050" on a typical board. Other people push power and ground closer together, in order to get *better coupling* between the power and ground planes. That would put the P-G spacing at about 0.005" (a factor of ten less).
Let's make the assumption that you are dealing with a board that has a P-G spacing of 0.050". This board, if fabricated with FR-4 dielectric, will have about 20 pF per square inch of natural interplane capacitance. If you are working with edge rates of about 1 nanosecond (500 MHz), then it is reasonable to assume that at any particular time, a disk of capacitance with a radius of about 1" is working in your favor as a conduit of interplane current. The effective amount of capacitance in the vicinity of the ends of your trace is therefore approximately [pi*(1")^2]*20pF= 63pF. The impedance of this structure at a frequency F of 500 MHz (corresponding to 1-ns rise times) is: 1/(2*pi*F*C)= 5 ohms.
Over shorter intervals of time, the signal has less of a chance to spread out, and the effective interplane impedance is greater; averaged over longer intervals, it is less. In other words, the interplane capacitance becomes less and less effective as we go up in frequency. In the limit, we will all someday need much smaller interplane spacings.
OK, so we have a number of 5 ohms for the effective interplane impedance, as measured at any particular spot on the board, when using 1-ns risetimes.
Next let's look at the bypass capacitors. Making the rash assumption that we have an array of bypass capacitors located on 1" centers, I can predict that about 4 of them will be within an inch of your signal injection point. Let's further assume (as long as we are going way out on a limb here) that the layout on each bypass component contributes an effective series inductance of 2 nH per part. The total effective impedance of the bypass path is therefore:
2*pi*(500 MHz)*(2 nH)/(4 parts) = 2 ohms
Wow! We learned that for such a wide interplane spacing, well laid out bypass capacitors form the majority of the interplane current path at frequencies in the range of 500 MHz. We didn't show it, but the bypass capacitors also win at other, lower frequencies. Above about 2 GHz, the board I have described will fall completely apart.
I hope this brief sketch gives you some idea as to how to analyze your situation. If you want to really get into the math, I seem to recall that the exact form of the solution for the propagation of a cylindrical wave between a power and ground plane is some kind of Bessel (yuk) function.
Dr. Howard Johnson