Article

Step Response Test

High-Speed Digital Design Online Newsletter: Vol. 11 Issue 01

I love a good question. It inspires me to write. This month Rashid asks something simple, the best kind of question, and one to which I hope I can deliver an adequate response.

His question relates to my previous article, "Eye Don't Like It", first published in EDN magazine November, 9, 2006. EyeDontLikeIt.htm

Step Response Test

Rashid writes:

Your recent EDN article "Eye Don't Like It" points out that an eye diagram makes a terrible diagnostic tool. The eye is good for checking margins in a finished system (it's a good compliance measurement) but a poor diagnostic tool. I got that part.

Then you go on to recommend a "step response test" as a better diagnostic tool, but don't say anything about how to use it. How do I do this test? How do I interpret the results?

Thanks,
Rashid

Dr. Johnson replies:

Thanks for your interest in High-Speed Digital Design.

The step response test is used to characterize a digital communication channel. In the lingo of channel testing, I assume you have a driver at the source, a long digital channel (trace, backplane, connector, or whatever) and a receiver at the far end, possibly including a termination.

For this discussion I set up an example channel using a National DS25BR100 driver. This LVDS-style driver has with 100-ps rise/fall times and adjustable transmit pre-emphasis. For this test the pre-emphasis is turned OFF.

The driver is conveniently mounted on a demo board (National DS25BR100EVK) with SMA connections going in and out of the driver chip and long microstrip traces that are easily probed. The output side of the driver, shown in Figure 1, is our "channel under test."

The layout works like this: The driver outputs (TX+ and TX-) connect first to a closely-spaced, tightly-coupled, 100-ohm differential pair. The trace spacing is dictated by the pin spacing on the driver package. The tightly-coupled pair runs for a distance of 0.5 inches away from the driver. After that short run the traces separate, making two independent, non-coupled, 50-ohm transmission lines. The purpose of separating the pair is so you can use fatter traces, reducing the skin-effect loss. The separate traces each run 1.7 inches to the SMA output connectors.

At the output connectors I attach 50-ohm semi-rigid low-loss coaxial cables that lead to channels 1 and 2 of a LeCroy SDA 6020 scope. The cables are 24 inches long (SCA type 52141).

I set a LeCroy D600A-AT differential probe at the point indicated. The thin solder mask layer is scraped from the top of the microstrip traces to permit probing.

Let's begin by looking at the complete eye pattern (Figure 2). This eye shows a compilation of all patterns of 9 bits (512 patterns in all). The data rate is 2.5 Gb/s (400 ps baud interval).

In the eye diagram, the worst-case voltage margin offenses (marked in Fig. 2) stand out like low-hanging fruit within the eye opening. The jitter is also obvious.

Although this signal could easily be used to transmit reliable data, it does not meet my expectations for signal quality right out of a driver. This low-jitter driver should look better.

To understand what's wrong in this circuit, you can peel apart the eye, looking at each pattern individually. The most useful pattern is a simple, one-time step. The result of transmitting such a step through the channel is called the step response of the channel.

Of course, a single step response would be impossible to accurately measure unless your scope has a sufficiently high sampling rate in real-time mode. My SDA 6020 can go to 20 Gs/s (50 ps per sample) in a single-shot measurement. That's pretty fast, but I want 5-ps resolution for my 100-ps rising and falling edges, so I'll use the random-interleaved sampling mode (RIS). That mode samples the signal multiple times, slightly offset in time at each repetition. RIS mode effectively collects information on a much more finely-grained grid of time points than would be possible in a single-shot acquisition. Other scope manufacturers may call this feature a "non-real time mode" or "sampling scope mode" or "equivalent time mode".

The disadvantage of RIS mode is that your signal must be repetitive in order for that measurement technique to work. Fortunately, I have full control over the channel measurement test signal, so I can make it repetitive. Once you have a repetitive stimulus, you can use a vertical averaging feature to knock down any random noise effects not correlated with your rate of stimulus, leaving a beautifully clear, pristine picture of the system step response. For the pictures shown here, I use 16x averaging.

My favorite repetitive step response stimulus is a simple square wave with 50% duty cycle. I generate this signal with an old HP8082A pulse generator. It has differential outputs with adjustable output levels and signal rise/fall times. That generator can dial up a square-wave signal compatible with just about any logic family.

If you have a square-wave source, connect it to your system. Adjust the source so that the driver forces a square-wave pattern into the channel with the same rise/fall time, and same output impedance, that will be used in the real system.

If you don't have a square wave generator, or can't attach one within the physical confines of your system, you can sometimes accomplish the same thing by programming your data transmitter to send a repetitive pattern like this:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1…(repeat)

However you generate the square-wave pattern, make the runs of HIGH and LOW sufficiently long that they elicit the full step-response of your system. After each edge, the response should flatten out to a smooth line before the next edge occurs. As a rule of thumb, assume it takes at least three round-trip times in your system for the response to flatten out after each stimulus.

If your data transmitter is coded, so that it cannot put out a sufficiently slow square wave pattern, try turning down the clock frequency until you get something slow enough to elicit the whole system response after each edge.

If the system is AC coupled, you must also make the runs of HIGH and LOW sufficiently short that the whole pattern passes through any DC-blocking capacitors, transformers, or high-pass filters that may exist in the channel.

Figure 3 shows two waveforms, both measured at the differential probe position. The blue waveform is the response to one particular pattern. That particular pattern happens to generate the worst ISI in the center of any baud interval.

The red waveform shows the step response. Each rising edge of the step response (red waveform, at A) elicits a negative bump located 400 ps later (red waveform, at B). Regardless the value of subsequent bits, that negative bump exists and will superimpose upon subsequent waveform events.

The superposition causes jitter. To see why, consider the two cases in Figure 4.

In blue, an isolated negative transition occurs at point B, where the signal has been at logic HIGH for a long period of time prior to B and then transitions down one and only one time at point B.

In red, a negative transition at B is preceded by a positive step at A.

The isolated negative transition gives a correct "true" negative transition at B, unaffected by residual ringing from previous events. The second case gives the same transition at B, but superimposed upon that waveform is the negative bump from the positive transition at A. The negative bump has the effect of advancing the apparent transition time at B, causing jitter. It's difficult to work that out from the eye pattern (Figure 2), but it you look carefully you might see that early transitions are always preceded by transitions of the opposite polarity in the previous bit cell. The later "normal" transitions are preceded by no transition in the previous bit cell.

I like the step response test because it makes clear the relation between each edge, and the subsequent interference it causes.

Next comes the cool part of step analysis. We know a negative bump exists. It is located about 400 ps after each main edge. Only a few structures can form such a bump:

(1) At some point upstream of the probe location, a double reflection between two circuit elements located 200 ps apart.

(2) A single reflection from a circuit element located 200 ps downstream from the probe location.

(3) An imperfection in the driver.

(4) An imperfection in the probe, its cable, or the scope.

Of all the possibilities, I discount (3) and (4) for the simple reason that I know, from previous testing, that the driver can generate, and the scope can observe, clean rising and falling edges with none of the 400-ps bump exhibited here. Still, I list these possibilities to remind you that, in the absence of other prior knowledge, they must be considered.

What we must look for, then, are two circuit elements separated by a round-trip distance of 400 ps.

Regarding (1), the probe sits 0.87 in. from the driver. Assuming a microstrip delay of 160 ps/in., that makes a total round-trip delay of:

2(0.87 in.)(160 ps/in.)=278 ps

That's not enough to account for a 400-ps delay. Rule out (1).

Regarding (2), the SMA connector sits 1.43 in. downstream from the probe. Between probe and connector the round-trip delay is:

2(1.43 in.)(160 ps/in.)=457 ps

Looking back at the step response, the center of the negative bump occurs slightly after the 400-ps mark on the chart. That timing lines up closely with our back-of-the-envelope calculation for the probe-to-connector round trip time. 

Preliminary conclusion: the negative bump may be coming from the SMA connector. See how easy that is! Just by analyzing the exact time the bump occurs, you can begin to pinpoint your sources of difficulty.

Next steps:

(A) Perform experiments to verify this conclusion.

(B) Decide whether it affects system performance.

I'll talk about those points next time. Right now, I've got to get ready for my next trip, April 28-May 1 in Washington, DC, where I'll present for the first time my all-new seminar,

High-Speed Noise and Grounding.

This course will be preceded by the ever-popular introductory course, High-Speed Digital Design.

 

The new course results from collaborations with many groups over the past years working with mixed-signal systems involving high-speed digital electronics used in conjunction with sensitive analog circuits such as radio receivers, GPS devices and cell phones. This course addresses the critical issues of noise and grounding that are seen in many advanced signal processing applications today, including avionics, telemetry and guidance systems. The main focus is on identifying and solving crosstalk problems within a system.

Best Regards,
Dr. Howard Johnson