November 22, 5:45 am
Ernie awoke with a start. It was still dark outside. His muscles tensed. Then,
slowly, as his mind returned to consciousness, he began to relax. He always felt this way the
morning after an all-night session in the lab—especially a session in which he'd discovered
something important. He always feared that he would forget everything before he had a chance to
write it all down and that his insight, his brilliant flash of inspiration, and the truth would
melt away with the sun's first rays.
It didn't. The ugly truth was still with him. Nothing was left to do now but craft his final message. Ernie stumbled into the kitchen to put on some coffee. Grumbling, he logged onto the main e-mail server and began...
Nov 22, 6:22 am
TO: Messrs Ulrich (VP Eng), Dagbottom (VP Mktg), Blumpf (Pres)
RE: Daily status report—Day 39
I have isolated our product failures to the layout of the daughterboard connector. Whenever the main data bus switches from mostly zeros to mostly ones, crosstalk within the connector activates the "write" strobe on the main-system EEPROM circuits. This failure is repeatable. It explains the slow degradation of our system performance, especially the failures to reboot (due to corruption of the EEPROM configuration data).
Last night, I finally pinpointed the source of the problem. I used a pulse generator to transmit some test signals through the connector, simulating the same voltage and current conditions that would exist during an actual bus transition. Assuming that my measurements are correct, in actual use, the connector will induce an aggregate crosstalk of more than 2V on the EEPROM write line.
This amount of crosstalk was not supposed to happen. It is the result of a monumental grounding error. As you know, the daughterboard connector includes many ground pins. During the layout phase, I inspected the layout artwork and film to ensure that these pins were properly connected to the ground plane beneath this connector (Figure 1a).
Unfortunately—for reasons I do not totally comprehend—the fabrication shop did not build our boards according to the layout specification. I can demonstrate the problem by cutting the board along the dotted lines in Figure 1b. If our boards were any good, the ground would remain electrically connected through the multiple ground pathways between pins. It doesn't. The clearance holes are too big. We'll have to order new boards.
My recommendation is that we immediately order a rush quantity of new boards and race to salvage at least a portion of our Christmas-deadline shipments. I regret that it has taken so long to resolve this problem. Because I couldn't directly see the inner layers, I assumed that the fabrication shop had built the board the way we asked.
Nov 22, 7:21 pm
Our board vendor says that his company has always adjusted the trace widths, pad sizes, and clearances to meet our trace-impedance and finished-yield targets. He suggests that in the future you ask to check the finished film that they actually use after panelizing, instead of the film from our layout department. Alternatively, you could ask to see some preliminary unlaminated panels, which show the finished etching on the inside. X-ray services are also available to help you see the inner layers.
I hope this information will be useful to you in your next job. Because we will now surely miss the Christmas deadline, our board has voted to shut down your project. I hope you don't take the board's action personally. The board vendor says that mistakes like this one happen all the time.