## Terminator III

My last column showed how the capacitance of a receiver loads an end-termination resistor, preventing the termination from doing its job. I used an isolation resistor (Figure 1), to partially decouple the effects of receiver capacitance from the termination and obtained a modest benefit. For now, ignore components T1 and L1. Assume that the external 50-Ω end-terminating resistor connects directly to the terminating bias voltage, VT. The FPGA-circuit model includes a short length of BGA-substrate trace plus the 9-pF capacitance of the die. Isolation resistor R2 brings into play a fundamental trade-off. Make the value too small, and the receiver capacitance, CIN, loads down the termination, which results in massive reflections. Increasing the value of R2 reduces the reflections but at the cost of degrading the signal rise time.

The goal of this column is to force the apparent termination impedance to equal precisely 50 Ω with minimum degradation of the received-signal rise time. Such a goal is made possible by using the concept of reciprocal impdances.

Two impedances are said to be reciprocal if, in the context of some pre-defined signal impedance Z0, the product of the two impedances equals (Z0)2. For any impedance A(f), you calculate the reciprocal impedance as B(f)=Z02/A(f). For example, in a circuit with Z0=50 Ω, a 9-pF capacitor and a 22.5-nH inductor should be reciprocal impedances, which you can check by simple multiplication:

(1/(j2πf(9×10-12))(j2πf(22.5×10-9)) = 2500 = (Z0)2

The factors of "j" and f in the calculation are critical to understanding reciprocal impedance. If you are stil with me, check your understanding by proving the following assertion.

[(Z0+A) || (Z0+B)] = Z0

Where

• A and B are assumed reciprocal with respect to impedance Z0, and
• The symbol "||" implies a parallel combination, (X || Y) = (XY)/(X+Y).

The proof involves only simple algebra.

The assertion suggests that, if you have any impedance, Z0+A, you may stabilize that impedance by placing it in parallel with the special impedance, Z0+B, where B is the reciprocal of A. The impedance of the resulting parallel combination will precisely equal Z0 at all frequencies.

In Figure 1, the input signal strikes two parallel paths. The lower path comprises 50-Ω resistor R2 in series with some impedance A formed by the transmission line and capacitor circuit within the FPGA.

The upper branch comprises a second 50-Ω resistor in series with some impedance B formed by the transmission line T1 and inductor L1.

Here is where the magic happens. If T1 in the upper branch and the BGA trace in the lower branch both share the same characteristic impedance, Z0, both lines have the same delay, and the impedances L1 and CIN are reciprocal with respect to Z0, then impedances A and B will also be reciprocal. OK, that's difficult to prove, but if you can suspend your disbelief for just a moment, you may recognize that what we have in Figure 1 is a pair of reciprocal impedances Z0+A and Z0+B placed in parallel, which together create an impedance precisely equal to Z0 at all frequencies. Your simulator will show you that this is true.

Second-order parasitics associated with the inductor and vias in the design surely affect circuit performance, but, to first order, this beautifully compensated termination works perfectly. 