When you connect 50-Ω traces on two boards made from dissimilar fiberglass-laminate materials, will high-speed signals reflect due to the sudden change in board properties as they move across the connection interface? This question arises because, in most cases, the boards have different transmission-line geometries. For example, comparing two PCBs (printed-circuit boards) having the same layer thickness, one with a dielectric constant of 4.3 and the other with a dielectric constant of 3.5, the second board must use wider traces to obtain the same 50-Ω characteristic impedance as the first. The adjustment of trace width and height to accommodate dielectric materials is a normal part of PCB manufacturing.
At the point of connection, assuming a perfect butt joint between the boards with no intervening connector, the abrupt change in trace width throws the local per-unit-length values of inductance and capacitance into chaos. That scenario sounds terrible, but, fortunately, the disruption persists only a short distance on either side of the joint. If you move a couple of trace heights away from the joint in either direction, the local characteristic impedance reverts to its designed value of 50 Ω. Fortunately, high-speed digital signals do not care about the impedance at any one tiny spot. They care only about the effective characteristic impedance averaged under each signal edge as it moves through a transmission structure.
The “telegrapher's model” of a transmission line employs a similar averaging principle. That model comprises a cascaded ladder filter with discrete blocks, each having one series inductor and one shunt capacitor. As long as the delay of each block remains shorter than the signal's rise or fall time, the signal propagates through the circuit as if it were a continuous transmission pathway. The local impedance, if you could define such a thing, radically alternates from purely inductive to purely capacitive as your signal moves along. This fact causes no great difficulties as long as the average ratio of inductance to capacitance remains fixed. The number of blocks a signal edge spans as it moves through the structure represents in some sense the “length” of the edge.
Each signal edge in a PCB trace has a definite physical length equal to the rise or fall time (seconds) times its propagation velocity (meters per second). In British units, the way most engineers still design PCBs, the propagation delay associated with a board material having a dielectric constant of 4.3 works out to roughly 6 in./nsec. If your signal-edge transition time is 50 psec, then the physical length of that edge will be (0.050 nsec)(6 in./nsec) = 0.3 inches. At typical PCB dimensions, a 50-psec rising edge, spanning a length of 300 mils, looms much larger than the local disruption zone created by a perfect butt joint of two traces with dissimilar geometries.
Imagine a 50-psec signal edge sliding along the first PCB trace (Figure 1). Slide it halfway onto the next board. Now, freeze time. Consider the value of the average impedance under a signal edge as it sits straddling the interface. To the left of the joint, as you look deep into the first PCB, the impedance appears correct. Near the joint, an abrupt change in trace width may disrupt the local impedance. Looking farther to the right, you can see that the impedance returns to its designed value of 50 Ω. If the signal edge spans a length much greater than the size of the disrupted zone, the long sections of unmolested 50-Ω transmission on either side of the joint effectively wash out the relatively small disruption. In that case, the disruption causes no difficulties. You run into trouble only when you reach such high speeds that the physical length of your signal edge shrinks to a size comparable with the impedance disruption.
These observations apply only to situations in which the characteristic impedance remains the same on both sides of the interface.