Endpoint Distortion
Figure 1 depicts three common transmission-line scenarios: series termination, end termination, and bi-directional termination, respectively. In all cases the drivers are fast with negligible series output resistance. The capacitive loads represent the input capacitances of the CMOS receivers.
In the series-terminated case (top row), a step edge from the driver proceeds to the right, interacts with the load, and reflects back toward the driver. The capacitive load may create a strange-looking reflection, and it may distort the appearance of the received signal, but whatever bounces off the load returns to the driver termination and dies, never to be seen again. As a result, the receiver sees one step edge, possibly distorted but with no lingering aftereffects. Of all the things that could go wrong with a circuit, this glitch is not too bad.
The right side of Figure 1 illustrates the equivalent endpoint circuit that defines the nature of instantaneous signal distortion at the receiver in each case. In the top row, corresponding to the series-terminated case, the equivalent circuit comprises two components: a series resistance equal to the line impedance, and a shunt capacitance representing the input capacitance of the receiver (see Driving Point Impedance, EDN 14 May 2009).
The RC low-pass filter thus formed disperses the input rise time. It also delays the signal's time of arrival by an amount equal to the group delay of the filter, in this case Z0CIN.
If your native signal rise or fall time is much faster than Z0CIN, then the received signal just looks like the filter step response—a nice, clean rising edge with a 10 to 63rise time of Z0CIN. If, on the other hand, your native signal rise or fall time is slower than Z0CIN, the signal dispersion has little effect. If you look closely, however, you will see that the circuit delays the time of arrival of the signal's midpoint by the amount Z0CIN.
The middle row of Figure 1 illustrates an end-terminated circuit. On the right, it shows a parallel combination of two elements feeding the capacitive load: the transmission line and the end termination. If the the line is long compared to the rise or fall time of the driver, then in the short term the parallel combination of those two elements will equal half of Z0, making the load in this case respond much more quickly than before, causing less distortion than in the series-terminated case. The time constant associated with the RC filtering effect in this circuit is (½)Z0CIN, half that of the series-terminated case.
The good news about end terminations is that they respond quickly. The bad news is that the capacitive load interferes with the end termination, preventing it from doing its job. Upon receipt of each signal edge, the capacitive load reflects a short pulse back toward the driver. The driver has no termination, so it reflects the pulse a second time. The end of the line thus receives a small reflected pulse one round trip after each arriving signal edge.
When signal timing fidelity is of utmost importance, the end-terminated architecture provides the least risetime dispersion and the least variation in timing in response to a variable load capacitance. In exchange for its improved short-term response, the end termination suffers the possibility that its roundtrip reflections may interfere with subsequent bits.
The last row in Figure 1 shows the equivalent endpoint circuit for a common bi-directional architecture. The figure depicts a bi-directional system that transmits one way or the other at a time, not both. Each driver connects through a resistor to the long pcb trace in the middle. When the left-hand driver activates, it transmits a signal from left to right. In that mode the resistor at the left side of the circuit serves as a series termination device for the left-side driver. Coincident with transmission, the right-side driver must be placed into a tri-state (high-impedance) condition.
The component marked COUT represents the parasitic shunt capacitance of the right-side transceiver when placed in the tri-state condition. In this mode the resistor at the right side of the circuit serves no useful function. In fact, it degrades the signal quality because the signal current must traverse the right-side resistor before it can begin to charge capacitor COUT.
The overall effect at the right-side receiving location is that of a load capacitor fed by a series combination of the transmission-line driving-point impedance (Z0) plus the additional series resistor. Since in common practice the series-terminating resistors are both set to a value near Z0, the total impedance driving the capacitive load equals 2×Z0. Bi-directional circuits of this type exhibit the poorest signal risetime of the three possibilities shown in Figure 1, but with the advantage of permitting bi-directional operation.