Driving Two Loads
The split-tee configuration (Figure 1a, omitting R2 and R3) conveniently drives two CMOS receivers from one output. If you keep the stub traces connecting receivers IC2 and IC3 sufficiently short, the agglomeration of stubs and receivers at the end of the line acts as a single lumped-element capacitive load. Any reflections that bounce off this combination load return to the driver where source-terminating resistor R1 extinguishes them. The receivers, therefore, see only one event in response to each step change at the driver. The heavy capacitance at the end of the line may affect the rise time of that event, but the result is monotonic with no lingering residual reflections.
Figure 1—The split-tee configuration drives two CMOS receivers from one output.
Figure 2—Hidden within the split-tee configuration is an unconstrained resonance.
Sounds good, but how short must you keep the stubs? That decision depends on the rise time of the driver and the degree of balance between the load impedances. In general, I advocate limiting the stub delay to one-sixth the rise time, which usually works, but I always simulate it to make sure. The circuit also works with longer stubs, but as you stretch the limit, the circuit becomes increasingly susceptible to imbalance between the loads. Figure 1b illustrates the effect of such an imbalance.
Ignoring R2 and R3 for the moment, imagine you suddenly inject a positive step at IC2 and a simultaneous negative step at IC3. The signal from IC2 heads south toward IC3 while the signal at IC3 heads north toward IC2. These two signals propagate toward each other, simultaneously crossing at Point A. At this point, the voltages from the two signals, being opposite, perfectly cancel. No current couples onto the main trace at A. The two signals continue on their way, slamming into opposite ends of the stub traces, reflecting, and bouncing back and forth between IC2 and IC3. I call this scenario an unconstrained resonance.
The mode is unconstrained because the terminator at IC1 has no opportunity to damp the oscillations. As long as the system is perfectly balanced, the two opposite signals from IC2 and IC3 always perfectly cancel, coupling zero current onto the main trace. Resistor R1 sees nothing. If the loads at IC2 and IC3 are perfectly reactive, the reflections may continue for many cycles. This circuit works like a child's seesaw. Imagine two kids vigorously working the plank up and down. Standing at the fulcrum, you can't stop them. You have to stand near one end where the plank is moving to have any significant effect.
Given zero coupling between the desired signal-propagation mode (current through R1) and the IC2–IC3 resonance, your signals should theoretically never excite the IC2–IC3 resonance, so it should cause no problems. Unfortunately, the circuit is never perfectly balanced. For example, receiver IC2 in Figure 1a contributes 6 pF of loading, whereas receiver IC3 contributes only 4 pF. The reflections between IC2 and IC3 don't perfectly cancel. Coupling occurs between the current in R1 and the IC2–IC3 resonance, and the received signals exhibit the horrible ringing shown in Figure 1b (top traces, no resistors). As you can see, the resonant mode occurs at about 500 MHz, corresponding to the third harmonic of the 166-MHz clock. As the clock starts, the heavy third overtone builds to ridiculous levels, causing non-monotonic behavior and possibly double-clocking in the receivers.
To defeat the resonance, I've added 18Ω resistors in series with each receiver. That's just enough in this example to knock down the Q of the highly resonant IC2–IC3 mode, eliminating the wiggles in the output signal without unnecessarily degrading the received rise time (bottom traces, 18Ω resistors).
Any time you build a split-tee, always simulate the circuit with a maximal degree of imbalance. For CMOS loads, that scenario means using the maximum load capacitance at one receiver and the minimum (sometimes zero) at the other. Look at the step response to see whether an observable resonance exists. If it does, simulate the circuit with a clock waveform at that resonant frequency (or one-third or one-fifth of that amount). Small series resistors in series with each gate input can sometimes extend the length at which the split-tee safely functions.