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NOTE: Articles published after 2013 are available only with purchase of the Collection.
High-Speed Digital Design Seminar.
About the Seminar (11/8/2015): 0.0-0.0.
[EE basics, management] A practical two-day seminar course about building high-speed digital hardware. It is filled with examples, explanations, and classroom demonstrations. Anyone who works with high-speed digital signals will understand and benefit from the material presented.
High-Speed Digital Design Book.
About the Book (11/8/2015): 0.0-0.0.
[EE basics, management] Considered the original "bible" of high-speed design issues, High-Speed Digital Design focuses on a combination of digital and analog circuit theory. This comprehensive volume helps engineers who work with digital systems shorten their product development cycles and fix their latest high-speed design problems.
High-Speed Noise and Grounding Seminar.
About the Seminar (11/8/2015): 0.0-0.0.
[EE basics, management] This course focuses on mixed-signal applications involving high-speed digital electronics used in conjunction with sensitive analog circuits such as radio receivers, GPS devices and cell phones. This course addresses the critical issues of noise and grounding that are seen in many advanced signal processing applications today, including avionics, telemetry and guidance systems.
High-Speed Signal Propagation Seminar.
About the Seminar (11/8/2015): 0.0-0.0.
[EE basics, management] This is an advanced-level course for experienced digital designers who want to press their designs to the upper limits of speed and distance. Focusing on lossy transmission environments like backplanes, cables and long on-chip interconnections, this two-day course teaches a unified theory of transmission impairments that apply to any transmission media.
High-Speed Signal Propagation Book.
About the Book (11/8/2015): 0.0-0.0.
[EE basics, management] This is an advanced-level reference text for experienced digital designers who want to press their designs to the upper limits of speed and distance.
High-Speed Digital Design: Opening Lecture.
HSDD Seminar (2015): 1.1-1.5.
[EE basics, management] Definition of Signal Integrity. Relation to EMI. Purpose of Studying Signal Integrity. Overview of Program. (9 min.) Movie SD Movie HD
HSDD Seminar (2015): 1.11-1.27.
[capacitance, EE basics, inductance] Your Schematic shows only the intended flow of signal power. Currents Form Loops. Every Loop of Current Has Inductance. Behavior of Inductance. Impedance Magnitude of Inductor. Effect of Inductor. Importance of Returning Current Path. Proximate Conductors Share Capacitance. How Capacitors Behave. Impedance Magnitude of Capacitor. Effect of Capacitor. Approximate Values of Capacitance. Practical Circuits are Littered with Parasitic Elements. (38 min.) Movie SD Movie HD
Frequency Content of Digital Signals.
HSDD Seminar (2015): 1.28-1.41.
[bandwidth, EE basics, ringing, rise time] Data Band. Baud Interval Band (Rectangle = Step). Rising/Falling Edge Band. Frequencies That Matter for Digital Design. Meaning of "Frequency Response". Effect of Parasitics. Conceptual Frequency Response of Every PCB Trace. Relation of Knee Frequency to Circuit Performance. Effect of Shrinking Rise/Fall Time. International Technology Roadmap for Semiconductors (ITRS). (25 min.) Movie SD Movie HD
Effects of Delay.
HSDD Seminar (2015): 1.42-1.59.
[delay, layer stack] Propagation Delay in Various Media. Example of Mixed Dielectric. Dielectric Properties of PCB Traces. Outer-Layer PCB Traces Are Faster. Distributed vs. Lumped Systems. Physical Length of Rising Edge. Pi Model of Transmission Line. Uses for The Pi Model. (52 min.) Movie SD Movie HD
HSDD Seminar (2015): 1.60-1.81.
[capacitance, crosstalk, inductance] Step Response Theory. How Resistive Loading Changes Circuit Delay. Mutual Capacitance and Mutual Inductance. Measurement of Mutual Coupling. Comparison of Inductive and Capacitive Crosstalk. A Faraday Cage Fixes Capacitive Coupling. Mutual Inductance is a Current-Flow Problem. Improving the Return Path Fixes Inductive Crosstalk. Why Many Engineers Think First About Capacitance. (38 min.) Movie SD Movie HD
Path of RF Current.
HSDD Seminar (2015): 1.82.
[inductance, returning signal current, SiLab HSDD] Experiments at 1 and 10 MHz demonstrate the effect of circuit layout on the flow of current. (11 min.) Movie SD Movie HD
Properties of Gates.
HSDD Seminar (2015): 2.1-2.10.
[ground bounce] Voltage Margin Budget. SSO Noise (Ground Bounce). SSO Test Setup. Theory of Operation. How SSO Noise Affects Inputs. (23 min.) Movie SD Movie HD
Factors That Reduce Ground Bounce.
HSDD Seminar (2015): 2.8-2.17.
[differential signaling, ground bounce, power systems, split planes] A Well-dispersed Array of Pwr/Gnd Pins. Differential Inputs. Shared Reference. Split-Power Architecture. (10 min.) Movie SD Movie HD
Scope Probes and Loading.
HSDD Seminar (2015): 3.1-3.9.
[capacitance, probes] FET-input probe. Differential Active Probe. Resistive-input probe. Input Impedance of Probes. Effect of Probe on Signal Under Test. Which Probe is Best? (13 min.) Movie SD Movie HD
Spurious Magnetic Interference.
HSDD Seminar (2015): 3.18-3.25.
[crosstalk, probes] Measuring Your Noise Floor. Probe Shield Currents. Differential Probing. Probing Without Ground. (12 min.) Movie SD Movie HD
HSDD Seminar (2015): 4.4-4.7.
[characteristic impedance, transmission line] Response to Step Input. Ice-Cube Tray Analogy. Equivalence of Z0 and RTERM. (15 min.) Movie SD Movie HD
Effects of Source and Load Impedance.
HSDD Seminar (2015): 4.11-4.17.
[termination, transmission line] Exponential Decay. Time-Space Diagram. Ways to Achieve Signal Convergence. (22 min.) Movie SD Movie HD
Un-terminated Line Examples.
HSDD Seminar (2015): 4.20-4.30.
[circuit topology, overshoot, ringing, transmission line] Example: Source Impedance Too Low. Example: Source Impedance Too High. (22 min.) Movie SD Movie HD
How Solid Plane Layers Control Crosstalk.
HSDD Seminar (2015): 5.1-5.10.
[crosstalk, reference planes, transmission line] Early Computers vs. Multilayer PCB. Microstrip Response to Changing Magnetic Field. Magnetic Field Animations. Do Not Give Your PCB Vendor Full Control Over H and W. How Much Crosstalk Can You Take?. Where Simulation Fails Us. (21 min.) Movie SD Movie HD
The Path of Returning Signal Current.
HSDD Seminar (2015): 5.12-5.17.
[reference planes, returning signal current, transmission line] The High-Speed Path Can Look Pretty Strange. Distribution of High-Frequency Current Underneath a Signal Trace. What about Capacitance?. Crosstalk Versus Trace Separation Experiment. Crosstalk Over a Solid Ground Plane (waveforms). Crosstalk Over a Solid Ground Plane (graph). (21 min.) Movie SD Movie HD
Ground Plane Slots.
HSDD Seminar (2015): 5.24-5.32.
[crosstalk, reference planes, returning signal current, transmission line] Traces Passing Over a Ground Plane Slot. Crosstalk From Ground Plane Slots. Connector Layout Slots. Crosstalk Versus Trace Separation Experiment. Crosstalk Over a Slotted Ground Plane (waveforms). Crosstalk Over a Slotted Ground Plane (graph). Why Wasn’t the Lower Plane Very Effective? (20 min.) Movie SD Movie HD
HSDD Seminar (2015): 5.33-5.42.
[crosstalk, guard trace, layout] Power and Ground Fingers. Cross-Hatched Ground Grid. Guard Trace on a Two-Layer Board. Guard Trace on Multilayer Board (classroom demo covers slides 5.37 - 5.42). (15 min.) Movie SD Movie HD
Split Power Planes.
HSDD Seminar (2015): 5.43-5.46.
[crosstalk, layout, power systems, split planes] Crossing a Split Power Plane Boundary. Use of Stitching Capacitors. Measuring Split-Plane Crosstalk. (8 min.) Movie SD Movie HD
Crosstalk NEXT and FEXT examples.
HSDD Seminar (2015): 5.55-5.66.
[crosstalk, examples] Measuring NEXT and FEXT. Effect of trace length, height, and separation. Stripline FEXT. Effect of terminations..
Overview of Termination Types.
HSDD Seminar (2015): 6.1-6.3.
[ringing, termination, transmission line] Systems that suffer ringing benefit from termination. Over-damped circuits do not. (8 min.) Movie SD Movie HD
HSDD Seminar (2015): 6.4-6.15.
[circuit topology, termination] Function of Split Termination. Design Constraints. Thevenin Equivalent Model of End Termination. Design Process. Design Solution. Reflections from a Capacitive Load. Effect of Stub Hanging Beyond End Termination. (36 min.) Movie SD Movie HD
Series Termination (Source Termination).
HSDD Seminar (2015): 6.16-6.27.
[circuit topology, termination] Halving and Doubling of Signal Amplitude. Value of External Series Resistor. No Clock Receivers Allowed in Middle of Series-Terminated Line. What’s That Plateau?. What’s That Glitch?. Heavy Capacitive Loads on Series and End-Terminated Lines. How Close Must a Series-Terminator Be to the Driver? (27 min.) Movie SD Movie HD
Comparison of Termination Styles.
HSDD Seminar (2015): 6.29-6.41.
[circuit topology, examples, termination] End Termination. Series Termination. Power Dissipation. AC Termination. Transmission Line States. Dynamic Termination. Proper Design of AC Termination. Comparison of Terminations (chart). Double-series termination. (39 min.) Movie SD Movie HD
Effect of Capacitive Loads.
HSDD Seminar (2015): 6.42-6.52.
[capacitance, circuit topology, reflections] Single Load in Middle of Line. Multiple Loads. Slowing Down the Rise Time. Adjusting the End Termination. Key Equations. Idea for Design. (20 min.) Movie SD Movie HD
End-Termination of Differential Signals.
HSDD Seminar (2015): 6.66.
[circuit topology, differential signaling, termination] Differential and common-mode termination concepts. (8 min.) Movie SD Movie HD
Gigabit Ethernet Examples.
HSDD Seminar (2015): 6.74-6.82.
[dielectric loss, dispersion, examples, reflections, skin effect, transmission line] Serial interface at 1.25 Gb/s. Showing dielectric loss and skin effect. Showing effect of vias and mismatched terminations. Showing effect of both-ends termination vs. single-end.
HSDD Seminar (2015): 8.14-8.19.
[bypass capacitors, examples, inductance, layout] Surface-Mounted Configurations. Inductance of Surface-Mounted Layouts (table). New Surface-Mounted Packages. AVX Interdigitated Capacitor (IDC). (6 min.) Movie SD Movie HD
Arrays of Capacitors.
HSDD Seminar (2015): 8.20-8.26.
[bypass capacitors, power systems] Modeling a Complete Power System. Dual-Value Capacitor Arrays. Choose the Smallest Package and the Biggest Value. (21 min.) Movie SD Movie HD
High-Speed Noise and Grounding: Opening Lecture.
HSNG Seminar (2015): 1.1-1.5.
[EE basics, management] Definition of Noise and Grounding Subject Matter. Purpose of Studying Noise and Grounding. Overview of program. (4 min.) Movie SD Movie HD
HSNG Seminar (2015): 1.11-1.20.
[crosstalk, EE basics, mixed signals] PCB Ground Plane Resistance. Slots in the Ground Plane Control the Flow of Audio-Frequency Current. Can a CPU Draw Audio-Frequency Currents?. Example of Entangled System. (28 min.) Movie SD Movie HD
HSNG Seminar (2015): 1.21-1.30.
[capacitance, examples] Current Flows in Loops. Return Path for an Antenna. Measuring Capacitance. Handheld Capacitance Meter. Example: Capacitance of Scope Chassis to Earth. Approximate Values of Capacitance. (14 min.) Movie SD Movie HD
HSNG Seminar (2015): 1.31-1.52.
[examples, inductance] Current Does Not Flow Instantaneously. Every Loop Has Inductance. Simple Inductance Test Circuit. Inductance of Circular Loop (Empirical). Inductance of Hairpin and Other Structures. Inductance of Wire Above Solid Plane. Why All the Fuss About Inductance?. Mutual Inductance Matters. What About Electromagnetic Radiation? (27 min.) Movie SD Movie HD
Main Points Not Taught in College.
HSNG Seminar (2015): 1.53-1.56.
[back plane, differential signaling] Logic Gates Are Differential Amplifiers. Digital Signals Have a Limited Bandwidth. Frequencies That Matter for Digital Signals. (9 min.) Movie SD Movie HD
HSNG Seminar (2015): 1.57-1.88.
[crosstalk] Level of Acceptable Crosstalk. Effect of Limited Package Bandwidth. Five Ways to Reduce Crosstalk:. Shrink the Aggressor. Reduce the Coupling. Change the Timing. Improve the Receiver Margins. Reduce the Number of Simultaneous Aggressors. Crosstalk is Highly Directional. (53 min.) Movie SD Movie HD
Distributed Nature of Inductance.
HSNG Seminar (2015): 2.1-2.22.
[ground bounce, inductance] Difficulties with Observing Ground Noise. Implications for Measuring Voltages. Example Measurement: Inductance of Via. (20 min.) Movie SD Movie HD
BGA Ground Ball Placement.
HSNG Seminar (2015): 2.26-2.76.
[chip packaging, crosstalk, ground bounce, SiLab HSNG] Measurement of BGA ball inductance. Effect of layout on measured values. Implication for ball pinouts. (35 min.) Movie SD Movie HD
Returning Signal Current at AF versus RF.
HSNG Seminar (2015): 3.1-3.4.
[reference planes, returning signal current] Distribution of High-Frequency Current Underneath a Signal Trace. (9 min.) Movie SD Movie HD
HSNG Seminar (2015): 3.29.
[crosstalk, testing] Crosstalk Over a Solid Plane. Measuring Tiny Amounts of Crosstalk. Three Ways to Control Unwanted Current. Example: Common-Mode Choke. Example: Current Shunt. Example: Change the Circuit Topology. (34 min.) Movie SD Movie HD
A Solid Plane Is Your Best Defense.
HSNG Seminar (2015): 3.30-3.36.
[crosstalk, reference planes] Your Reference Plane Is Not Perfect. Fast-Changing Magnetic Flux Passes Underneath Every PCB. (9 min.) Movie SD Movie HD
Perspective and Vertical Height.
HSNG Seminar (2015): 3.37-3.46.
[connectors, EMC, layout] Enchanted Rock (story). Example: Marshall LCD-15 Video Monitor. Consequences of stacking connector. (13 min.) Movie SD Movie HD
Power Plane Segments.
HSNG Seminar (2015): 3.48-3.51.
[ferrite beads, layout, power systems] When to Segment the VCC Plane. Power Region Placement. About Ferrite Beads. Information Required to "Design" Power Filter Network. (22 min.) Movie SD Movie HD
Moat and Drawbridge Construction.
HSNG Seminar (2015): 3.52-3.55.
[crosstalk, mixed signals, returning signal current, split planes] Efficacy of Ground Cuts at RF. The Cut Does NOT Eliminate RF Crosstalk. (14 min.) Movie SD Movie HD
HSNG Seminar (2015): 4.1-4.13.
[crosstalk, grounding, returning signal current] Immutable Law of Development. Difficulties Understanding Orders of Magnitude. Difficulties Imagining Behavior of Solid Sheets of Copper. Picture Frame Analysis: a New Way of Thinking. Principle of Single-Point Grounding. A Common Grounding Mistake. Principle of Moat and Drawbridge Construction. Single-Point Connection to Chassis. Double-Connected Analog Region. But, I Did the Bad Thing and It Worked!. (12 min.) Movie SD Movie HD
Three Ideas for Audio-Frequency Isolation.
HSNG Seminar (2015): 4.14-4.22.
[crosstalk, grounding, mixed signals, split planes] High Impedance Blocks Unwanted Current. Low Impedance Shunts Current Away. Change the Topology. Example: ADC Grounding. Moats for Multiple ADCs. Align Each Moat with Its Special Power Region. Moats and Floats: Your Chance to Experiment. (27 min.) Movie SD Movie HD
HSNG Seminar (2015): 4.23.
[crosstalk, examples, mixed signals, SiLab HSNG] Mixed-Signal Isolation, Part I, "Audio Examples". Crosstalk at audio frequencies. Mitigation strategies. (15 min.) Movie SD Movie HD
What’s Different at RF.
HSNG Seminar (2015): 4.24-4.46.
[layout, mixed signals] Overview of RF issues. Capacitance of planes. Inductance of wires. Structural resonance. Adequate grounding. (41 min.) Movie SD Movie HD
Interconnections Between Boxes.
HSNG Seminar (2015): 4.47-4.57.
[crosstalk, examples, mixed signals, SiLab HSNG] Adapted from Mixed-Signal Isolation, Part II: "RF Crosstalk" (live discussion) Coaxial Cables and Connectors. Test Arrangement for measuring crosstalk (slide 60). Extending the Dynamic Range of Your Scope. Increase Level of Aggressor. Example Measurement: Coaxial Shield Effectiveness. (17 min.) Movie SD Movie HD
HSNG Seminar (2015): 4.58.
[crosstalk, examples, mixed signals, SiLab HSNG] Mixed-Signal Isolation: Part II (continued): Measured crosstalk between two coaxial cables. (9 min.) Movie SD Movie HD
Imperfections in Shield Coverage.
HSNG Seminar (2015): 4.59-4.62.
[coaxial, grounding, shielding] Shielding Effectiveness (Shield-Current Transfer Impedance). Direct Attachment of Coax to Chassis. Coaxial Shield Circuit Theory. (17 min.) Movie SD Movie HD
Unexpected Synchronization Difficulties.
HSNG Seminar (2015): 5.1-5.9.
[data coding, differential signaling] What Happens When You Unplug a Link?. How To Detect Unplugged or Inoperative Links. Well-Balanced Plug-able Differential Interface. Killer Packets. Difficulties with Multi-synchronous Systems. (31 min.) Movie SD Movie HD
Common and Differential Modes.
HSNG Seminar (2015): 5.16-5.23.
[differential signaling, examples] Differential Example. Every Signal Comprises Two Parts. Why We Care About Modes. UTP Applications Require Extreme Common-mode Attenuation. Imbalanced Output Circuit. Example: Fast/Gigabit Ethernet Launch. (9 min.) Movie SD Movie HD
What is Jitter.
HSNG Seminar (2015): 5.26-5.40.
[jitter] Racing Game Analogy. Tracking Bandwidth. Definitions of Jitter. Jitter: a New Dimension. Why Jitter Matters. Causes of Jitter. Additive Noise. Vertical Shift vs. Timing Offset. Three Ways to Reduce Additive Jitter. Sources of Additive Noise. (21 min.) Movie SD Movie HD
Example Jitter Measurements.
HSNG Seminar (2015): 5.41-5.68.
[examples, jitter] Duty-cycle distortion. Effect of ringing. Effect of pair skew. Example of skew from DLL. Making a good low-jitter clock source. Jitter propagation.
HSNG Seminar (2015): 5.69-5.89.
[examples, jitter] National Semiconductor EVK board. Main Types of Jitter. Jitter Test Setup. Jitter Track. Jitter Histogram. Synchronizing the scope with power supply ripple. Sync with AUX (waveform). Sync with VCC01 (waveform). Sync with FM mod (waveform). (25 min.) Movie SD Movie HD
HSNG Seminar (2015): 6.1-6.12.
[coaxial, connectors, crosstalk, shielding] ERmetZD. Ground Transfer Impedance. Mutual Inductive Noise Coupling. Coaxial Shield Grounding. Ground Transfer Impedance. Examples. Ground Transfer Impedance Calculation. (12 min.) Movie SD Movie HD
HSNG Seminar (2015): 6.12.
[crosstalk, examples, mixed signals, SiLab HSNG] Mixed-Signal Isolation: Parts II-III, "RF Connectors" and "Achieving 120 dB Isolation": Showing the importance of a good ground attachment between the connector and your PCB. (20 min.) Movie SD Movie HD
PCB Traces at RF.
HSNG Seminar (2015): 6.12.
[crosstalk, examples, mixed signals, SiLab HSNG] Mixed-Signal Isolation: Part III "PCB Traces": Showing two traces on the same side of the same board, and what it takes to attain 120 dB isolation between the two traces. Effects of grounding, good connector layout, and shielding. (20 min.) Movie SD Movie HD
HSNG Seminar (2015): 7.1-7.13.
[testing] Compliance Testing vs. Debugging. An Eye Pattern is a Compliance Test. Example: 2.5 Gb/s Differential Link. Compilation of Eye Diagram. Worst Patterns are Clearly Visible Within the Eye. A Step Response is a Debugging Test. Compliance Testing: Interview with J. P. Miller. Debugging Procedures. Working with Very Pure Signals: SINAD. Working with Very Large Signals: ESD. (28 min.) Movie SD Movie HD
RoHS with Joe Fjelstad.
HSNG Seminar (2015).
[reliability, SiLab HSNG, soldering] Lead-free solder is not a "green" solution. Lead-free solder actually damages the environment more than 60/40 solder. System-reliability impact of lead-free solder. (21 min.) Movie SD Movie HD
(Advanced) High-Speed Signal Propagation: Opening Lecture.
HSSP Seminar (2015): 1.1-1.4.
[EE basics, management, serial link] Delineation of Material to be Covered. Prerequisites. Overview of Program. (5 min.) Movie SD Movie HD
Tools for Highly Optimized Work Above 1 GHz.
HSSP Seminar (2015): 1.15.
[management, probes, testing] Scope and probes. Vector network analyzer. Budget and time for multiple board spins. Ringing and Crosstalk (2D) simulator. Full-wave (3D) simulator. Power integrity simulation. (9 min.) Movie SD Movie HD
Review of Mathematical Fundamentals.
HSSP Seminar (2015): 1.16-1.20.
[bandwidth, EE basics, EM fields, rise time] Impedance and Bandwidth. Power Spectral Density of Digital Signal. 3-D Rule of Scaling—Lossless Circuits. 2-D Scaling of PCB Cross-Section. (25 min.) Movie SD Movie HD
Transmission Line Basics.
HSSP Seminar (2015): 2.1-2.11.
[characteristic impedance, transmission line] Telegrapher’s Model. RLGC Model. Meaning of "TEM" mode. Voltage and Current Waveforms on Lossless Line. Charges in Motion (animation). What happens after a Pulse "Leaves the Station?". (37 min.) Movie SD Movie HD
HSSP Seminar (2015): 2.12-2.30.
[attenuation, skin effect, transmission line] DC Series Resistance. DC Shunt Conductance. How Magnetic Shielding Works. The Walls of a Conductor Form a Shield. Skin Depth vs. Frequency for Copper. The Distribution of Current Changes With Frequency. High-Frequency Current Flows Only in a Shallow Band of Effective Depth d. High-Frequency Magnetic Fields. Paradox: Two Round, Symmetric Conductors. Proximity Effect. Popsicle-Stick Analysis. Proximity Effect for Differential Pcb Traces. Surface Roughness. Onset of Roughness Effect. Complete Resistance Model. (39 min.) Movie SD Movie HD
HSSP Seminar (2015): 2.31-2.37.
[attenuation, delay, transmission line] Microwaves Heat All Insulating Materials. Measurement of Dielectric Loss. Conduction Current and Displacement Current. Deterioration in Dielectric Constant. Complete Capacitance Model. Approximate Rule of Dielectric Mixtures. (17 min.) Movie SD Movie HD
TEM Transmission Media.
HSSP Seminar (2015): 3.1-3.7.
[dispersion, non-TEM, transmission line] Attenuation vs. Frequency (graph). Characteristic Impedance (graph). Approach to Modeling. General Properties. Is a Transmission Line Ever Not a Transmission Line? (demonstration). (15 min.) Movie SD Movie HD
HSSP Seminar (2015): 3.8-3.14.
[capacitance, inductance, reflections] Lumped-Element Modeling. Limits to Lumped-Element Analysis. Pi-Model for LC mode. Pi-Model Special Cases. Reflection Coefficients for Reactive Loads. Reflection From Capacitive Load (Derivation). (10 min.) Movie SD Movie HD
HSSP Seminar (2015): 3.15-3.20.
[attenuation, resistance, transmission line] Elmore Delay Estimation. Elmore Delay for Cascade of RC Networks. On-chip: Long-Haul Distribution. (6 min.) Movie SD Movie HD
HSSP Seminar (2015): 3.26-3.27.
[attenuation, dielectric loss, transmission line] Slope of loss versus frequency. Implication for speed and distance scaling. (3 min.) Movie SD Movie HD
HSSP Seminar (2015): 3.36-3.49.
[equalization, examples] PCB Trace Performance (graph). Received Signal at End of Line (waveform). Criteria for ISI Errors. ISI Criteria in the Frequency Domain. TTL/CMOS Levels Have Little ISI Tolerance. ISI Tolerance of Signaling Schemes. Time-Domain Response with 1st-Order Digital Equalizer. Digital Transmit Pre-emphasis Analysis. Effect of Equalization (1-m). Effect of Equalization (0.5-m). Digital EQ Eye Patterns for 10BASE-T Ethernet. Real backplanes. 4-Tap Transmit-Based Equalizer for PAM-4. (35 min.) Movie SD Movie HD
Analog Equalizer Examples.
HSSP Seminar (2015): 3.50-3.54.
[equalization, examples] Analog 1-Pole Equalization Circuit. Refinement for Constant-Impedance Input. Symmetric Equalizer. Balanced, Constant-Impedance Symmetric Equalizer.
HSSP Seminar (2015): 4.1-4.9.
[S-parameters] Why bother with the frequency domain?. Terminology of Frequency-Domain Analysis. Sine In, Sine Out. The advantage of LTI modeling. Information Necessary to Characterize an LTI System. Is a Digital Driver LTI?. Frequency-Based Analysis. (13 min.) Movie SD Movie HD
Scattering parameters (S-parameters).
HSSP Seminar (2015): 4.10-4.20.
[S-parameters] S-Parameter Test Setup. Wafer Probe Design. Transmission Lines are Symmetric. Do Not Cascade S21 Terms. Do Not Multiply S-Matrices. Proper S-Matrix Combination. Conversions Between Forms. Using S-Parameters with Spice. Good Applications for S-Parameters. (27 min.) Movie SD Movie HD
Linear System Theory (Supplemental).
HSSP Seminar (2015): 4.21-4.28.
[S-parameters] Theory of Linearity. Theory of Linear Superposition. Theory of Time-Invariance. Convolution. Comparison of Time- and Frequency-Domain Approaches.
HSSP Seminar (2015): 5.1-5.15.
[attenuation, examples, microstrip, stripline] Microstrip Examples. Stripline Examples. Resistive Loss Versus Trace Width. Nickel Plating. Passivation and Soldermask. Effect of Thin Soldermask Coating. Form of Specification for Laminates. Laminate Examples. How Far Can I Go?. Example: PCI Express 2.5 Gb/s. Example: RocketIO at 6.25 Gb/s. (25 min.) Movie SD Movie HD
Potholes (Transmission Line Imperfections).
HSSP Seminar (2015): 5.16-5.25.
[capacitance, inductance, reflections, transmission line] Reflection from a Capacitor. Reflection from a Short Hi-Z Segment. Compensation Idea. Example: Compensated Capacitance. Design Goal: Balance L and C. Limits to Applicability. (19 min.) Movie SD Movie HD
HSSP Seminar (2015): 5.26-5.41.
[connectors, crosstalk, EMC, reflections] Measuring Signal Fidelity. Measuring Crosstalk. Measuring Ground-Transfer Impedance (EMI). Examples of Backplane Connectors. ERmetZD, I-Trac. RF Connectors. Concept of Tapered Transitions. Practical Co-planar Waveguide Taper. Nearly Co-planar Waveguide (NPW) Taper. Simple Taper Example. RF Connector Sizes. RF Connector Comparison. (28 min.) Movie SD Movie HD
Inductance of PCB Via.
HSSP Seminar (2015): 5.44-5.51.
[examples, inductance, SiLab HSSP, vias] Conditions of Measurement. Path of Return Current. Measuring Incremental Parameters. Four-Terminal Inductance Measurement. Step-Response Measurement of Inductance. Measured Data. Impedance of a Via. (32 min.) Movie SD Movie HD
HSSP Seminar (2015): 5.52-5.63.
[characteristic impedance, layout, vias] Movie Quiz: Adjustments to Via Geometry. Shallow Blind Vias. Blind Via Capacitance (table). Inductance of Vias That Penetrate Multiple Planes. Via Inductance (example calculation). Stripping Via Pads on Unused Layers. Efficacy of Stripping Pads. (26 min.) Movie SD Movie HD
HSSP Seminar (2015): 5.64-5.73.
[layout, reflections, vias] Effect on Circuit Performance. Ways to Truncate Dangling Vias. Efficacy of Counter Boring. Wine-Glass Via. Oval Clearances. Differential Via with Oval Clearance. Differential Via with Extra Ground Vias. (31 min.) Movie SD Movie HD
Purpose of Differential Signaling.
HSSP Seminar (2015): 6.1-6.11.
[differential signaling, EE basics] Defeating Ground Bounce. Comparison of UTP and PCB Differential Applications. Differential Geometry on PCB. Distribution of Current in Edge-Coupled Microstrip. Differential Vocabulary. Modes of Propagation. Effect of Asymmetry. Vocabulary: Differential Peak-to-Peak Voltage. (30 min.) Movie SD Movie HD
Differential Receivers Tolerate High-Frequency Losses.
HSSP Seminar (2015): 6.22.
[attenuation, differential signaling] Effect of Receiver Thresholds on Signal Quality in the Face of Signal Dispersion. (3 min.) Movie SD Movie HD
Reducing EMI with Differential Signaling.
HSSP Seminar (2015): 6.24-6.25.
[differential signaling, EMC, examples] Analysis of When Tight Trace Spacing Might Affect Signal Radiation. (5 min.) Movie SD Movie HD
HSSP Seminar (2015): 6.34-6.35.
[circuit topology, differential signaling, termination] Common and Differential Modes of Termination. Achieving Both. (2 min.) Movie SD Movie HD
Routing Clocks and Other High-Speed Signals.
HSSP Seminar (2015): 12.1-12.14.
[clocks, layout] Special Requirements for Clock. Clock Repeaters are Built to Provide Multiple Low-Skew Clocks. Active Skew Correction. Clock Tree. Zero-Delay Clock Repeater. Point to Remember. Stripline vs. Microstrip Delay. Delay of Typical Microstrips. Importance of Terminating Clock Lines. Ringing on Short, Un-terminated Trace Distorts Timing. Ground Bounce Effect on Clock. Crosstalk. Advice on Routing Differential Clocks. (23 min.) Movie SD Movie HD
HSSP Seminar (2015): 12.15-12.19.
[clocks, delay, layout] Serpentine Coupling. Coupled Serpentine Waveforms. 24-Section Serpentine. Rules for Successful Delay Lines. (13 min.) Movie SD Movie HD
HSSP Seminar (2015): 12.20-12.34.
[multi drop] To Tee or Not To Tee. Basic Tee with No Termination. Add Receivers (and ESD Diodes). Tee with Slow Driver. Tee with Both-Ends Termination. Tee with Weak End Termination. Tee with Sneaky Impedance Adjustment. Tee with Series Termination. Unbalanced Tee with Series Termination. Unbalanced Tee with End Termination. Unbalanced Tee with Distributed Damping. Apply Your Knowledge: Check the "H" For Resonance.. (27 min.) Movie SD Movie HD
HSSP Seminar (2015): 12.35-12.45.
[multi drop] Example: Reflection Amplitude in Daisy Chain. Reflection Coefficient. Reducing the Impact of Tap Capacitance. Daisy-Chain Case Study. Using Five Loads of 3 pF Each. Squeeze Loads Closer Together. Why Overshoot Occurs. Change End Termination to 36 Ohms. Rules for Good Daisy-Chaining. Ironing Out the Bumps (2-in. Spacing). (24 min.) Movie SD Movie HD
Frequency Offset, Wander, and Jitter.
HSSP Seminar (2015): 12.46-12.59.
[clocks, jitter] Clock Recovery on a Serial Link. Clock Specifications. Why Are Oscillators Imperfect?. Effect of Frequency Offset in PLL Clock Recovery Circuit. Effect of Wander in PLL Clock Recovery Circuit. Racing Game Analogy for Understanding Tracking and Filtering Behavior. Your Tracking Filter. Decomposition of Trajectory. What’s Better?. Car vs. PLL. Tracking Gain vs. Frequency. Effect of Resonance on Cascaded Systems. Effect of Large Multiplication Ratio. SONET Clock Architecture. (35 min.) Movie SD Movie HD
HSSP Seminar (2015): 12.60-12.74.
[jitter, testing] Appearance of Jitter. Jitter Histogram. Decomposition of Jitter Histogram. Extrapolation of Random Jitter. Deterministic vs. Random Jitter. Extra for Experts: Jitter Measurement Techniques. Measuring Deterministic Jitter. Measuring Random Jitter. Combining Deterministic and Random Jitter. Fudge Factors for Random Gaussian Jitter. Time-Interval Analysis (TIA). Golden-PLL Method for Measuring Jitter. BERT Scan. Spectral Measurement of Jitter Variance. (19 min.) Movie SD Movie HD
Serial Link Architecture.
HSSP Seminar (2015).
[crosstalk, differential signaling, examples, layout, SiLab HSSP] Example of 10Gbps Serial Link. Introduction to System Modelling. Trace Layout. Crosstalk from Various Sources. (31 min.) Movie SD Movie HD
Serial Link Budgeting.
HSSP Seminar (2015).
[attenuation, back plane, differential signaling, dispersion, examples, reflections, SiLab HSSP] A Simple Signal Quality Budget. Discussion of PCB Transitions. Backdrilling. PCB Trace Losses. Signal Dispersion and the Effect of Equalization. (43 min.) Movie SD Movie HD
Why Reflections Happen.
[characteristic impedance, reflections, termination] Whatever impedance creates no reflection is DEFINED as the characteristic impedance of the transmission structure. There is no other definition.
[EM fields, grounding, probes, testing] When looking at a noisy, jittery signal, how can you tell which parts of the signal are "real" and which parts derive from noise and interference?
Lockheed Luncheon (3/15/2013): 0.0-0.0.
[management, probes, testing] Measurements define the body of knowledge we call Signal Integrity. Master the technique of making proper measurements and you will become a guru of the art.
Make It Better.
[characteristic impedance, ringing] When the driver output resistance in the falling direction must be less than the output resistance in the rising direction, a common situation in CMOS totem-pole drivers, no value of series-terminating impedance can possibly make both edges perfect.
PLL Response Time.
Newsletter v15_04 (12/10/2012).
[jitter, rise time] If you wish to clean up a jittery reference clock, removing the jitter, use a very low PLL tracking bandwidth. On the other hand, a serial data recovery application requires the highest PLL tracking bandwidth practicable.
Body and Soul.
[management] Even if you never master a musical instrument to the point of performing onstage, the simple act of learning to play music stimulates parts of your brain critical to creativity and insight.
[skin effect, testing] Nickel plating substantially increases the high-frequency resistance of a pcb trace. It lengthens the step response of the trace, exacerbating both inter-symbol interference and jitter.
Jitter Reference Clock Settings.
Newsletter v15_03 (8/21/2012).
[jitter, testing] You can never measure (or even define) the meaning of jitter in any absolute sense. All you can do is compare one signal against another and measure the difference in zero-crossing times between the two waveforms.
Newsletter v15_02 (5/17/2012).
[crosstalk] A guard trace, or guard track, is a pcb trace that is installed parallel to an existing high-speed signal. Guard traces are usually installed in the hope of reducing crosstalk.
Blocking Capacitor Performance.
[level translation, reflections, serial link] Cut a small round void in the reference plane layer right under the capacitor, thus relieving the capacitance to ground, while at the same time slightly increasing the series inductance.
Spotlight Interview with Dr. Howard Johnson.
[management] Dr. Johnson responds to questions from the EE Web staff about technology, it’s direction, the importance of early education, and the influence of parents and mentors. This article is reprinted in honor of his father, Dr. Jim Johnson, 1932-2012.
Winsome Waveform Wizardry.
[management] This fast-paced podcast appearance with Chris Gammel on the "Amp Hour" touches on many of the finer points of life, including how to hide technical details from your boss, how to get a standard through the IEEE, and dealing with unwelcome co-workers.
Quadrature Connector Layout.
[connectors, crosstalk, EM fields] Figure 1 illustrates the blueprint for a differential connector that radically reduces crosstalk between nearest-neighbor pairs.
Quadrature Via Layout.
[crosstalk, EM fields, vias] No matter where you place a differential via pair, you can always rotate its alignment to mitigate crosstalk from a troublesome differential source.
[management] Quality is not the result of comprehensive computer simulations. Quality is the result of knowing, through experience, how a product will actually be used in the field and anticipating those needs.
High-Speed Backplane Connectors.
EMC Soc (8/17/2011).
[back plane, connectors, crosstalk] Discusses the main factors affecting backplane connector performance, and predicts the future of backplane connector development.
High-Speed Digital Design: Overview Article.
[EE basics, management] This survey article highlights key similarities, and important differences, between high-speed digital and microwave hardware, addressing factors related to transmitters, transmission pathways, receivers, and the people who design them.
Newsletter v14_04 (8/10/2011).
[EE basics, transmission line] Charge carriers within a metallic conductor move under the influence of local electrical fields. Lacking any impetus to move; they remain still.
Whang That Ruler.
[ringing, termination] A capacitive load applied to a pcb trace lowers its resonant frequency much like a quarter taped to the end of a ruler lowers its resonant pitch.
Charge in Motion.
Newsletter v14_02 (4/3/2011).
[EE basics, transmission line] The slight compressibility of the sea of electrons in a metallic conductor generates most high-speed digital design effects.
Power of Attraction.
Newsletter v14_01 (2/11/2011).
[EM fields, returning signal current] Suspend a nickel in the air above the battleship Arizona. Remove all the conduction-band electrons from the nickel and place them on the battleship.
Fundametals of PCB Design.
[layout, power dissipation] This introductory overview of printed-circuit design treats the main difficulties you will likely meet when planning, designing, and manufacturing printed circuit boards for digital applications.
Newsletter v13_01 (3/19/2010).
[jitter, testing] If you want to measure jitter the same way your receiver sees it, program your jitter measurement equipment to mimic your receiver’s PLL tracking algorithm.
It’s a Gaussian World.
[bandwidth, rise time] My previous article, "Real Signals" (EDN Oct. 08, 2009), suggests that most digital output waveforms follow a nearly Gaussian profile. Let’s test that theory with a real-world measurement.
[rise time, sampled data] If you have a record of a driver’s actual output signal shape, or can extracted it from an IBIS file, use it. In the absence of other information, assume a Gaussian shape.
Newsletter v12_06 (10/8/2009).
[jitter, testing] Here is a simple and effective jitter-creation circuit you can use in your own laboratory to create calibrated amounts of jitter. Observing this source, you can try all the features of your jitter-measurement equipment to see what they all do.
[reflections, transmission line] When you connect two boards made from dissimilar fiberglass laminate materials, will high-speed signals reflect due to the sudden change in board properties as they move across the connection interface?
Comparing Transmission Media.
Newsletter v12_05 (7/26/2009).
[attenuation, transmission line] Transmission line comparisons may be complicated by various geometrical factors, but if you just remember that BIGGER conductors have LESS resistive loss you will have gone a long way towards understanding transmission line losses.
[reflections, termination] The tri-state feature, if available in your driver, acts as a sort of additional short-time dynamic memory element that you can use to extend the hold time of your driver.
[reflections, termination] The nature of instantaneous signal distortion at the receiver is defined by an equivalent circuit comprising two components: a series resistance and a shunt capacitance.
[reflections, termination] In a perfect series-terminated architecture, you can measure the driving point impedance at the driver, in the middle of the line, or a hundred miles away, the measurement always returns the same number: Z0.
Newsletter v12_04 (4/15/2009).
[back plane, transmission line] A current-source driver overlaps its own signal on top of other signals passing by without inhibiting their progress.
[management] You were the kid popping wheelies, probing the limits of unstable equilibrium. On the playground swing set, every jump tested your knowledge of gravity, the nature of inelastic collisions, and bruised ankles.
Newsletter v12_03 (3/26/2009).
[back plane, transmission line] A distributed bus simultaneously activates more than one driver. The timing on a distributed bus is as intricately planned as a ballet.
Newsletter v12_02 (1/25/2009).
[back plane, transmission line] Where the waves cross, at each point in time and space the transmission line sums their amplitudes. Like rogue waves crossing in the middle of the ocean, the effective total height of the combination may exceed that of either wave alone.
Newsletter v12_01 (1/9/2009).
[crosstalk, EM fields] Differential links have a good reputation for rejecting external noise. Unfortunately, that good reputation extends only to noise that affects both wires equally.
[characteristic impedance, differential signaling, reflections] The trick of inserting nearby compensation to fix problems elsewhere within the transition region is the secret to successful transition design.
Newsletter v11_06 (10/8/2008).
[jitter, testing] I wish I could begin by stating the definition of jitter. Wouldn’t it be great if there was only one definition? Unfortunately, the subject isn’t that simple. Here’s a sampling of definitions from various sources.
[characteristic impedance, differential signaling] When separation, S, is less than wire diameter, D, doesn’t your formula ln(2S/D) return a negative value for characteristic impedance? What gives?
Why is That?.
Newsletter v11_05 (9/2/2008).
[reflections, termination] You need three things: Good measurement equipment, a simulation system handles your application, and knowledge of what factors might reasonably affect your design. I teach the knowledge part.
All About Surface-Mount Ferrites.
[EMC, ferrite beads] Don’t use a ferrite bead unless you have data showing impedance versus frequency while under the influence of DC bias current, and don’t operate ferrite beads close to their maximum rated current.
Crossing the River.
[returning signal current, rise time, split planes] Cross a river without a bridge and your clothes get soaked. Cross a split-plane gap with a high-speed signal and your whole development schedule gets soaked.
EM Simulation Software.
[EM fields, EMC, simulation] Dr. Bruce Archambeault, distinguished engineer at IBM, IEEE fellow, and the author of the "EMI/EMC Computational Modeling Handbook", responds to my questions about electromagnetic (EM) simulation software.
[probes, testing] Some high-speed oscilloscope probes comes equipped with tips so pointy, so sharp, that you can set them down onto a pcb trace just as gently as a phonograph needle and still pick up a great signal.
Newsletter v11_03 (5/19/2008).
[bandwidth, probes, testing] A bandwidth-limit feature performs a service somewhat like vertical averaging, in that it reduces random noise, but it does not require a repetitive signal.
[microstrip, probes] I only know six ways to remove solder mask for probing: Scraping, milling, grinding, micro-blasting, chemical stripping, and ultraviolet (UV) illumination.
Designing a Split Termination.
[termination] A Thevenin equivalent circuit helps you understand the need for two resistor values and how they work together to meet the impedance and current-drive constraints imposed by your driver.
Confirm the Diagnosis.
Newsletter v11_02 (3/26/2008).
[connectors, probes, testing] The confirmation step is crucial because it takes a lot of time to do re-work, or re-layout, and you must be sure of your conclusions (3.125 Gb/s serial link).
Step Response Test.
Newsletter v11_01 (3/13/2008).
[connectors, probes, testing] My favorite repetitive step response stimulus is a simple square wave with 50% duty cycle. (This article includes many details of measurement technique and interpretation.)
Mixed-Signal Isolation: Part I.
HSNG Seminar (2008).
[crosstalk, grounding, mixed signals, SiLab HSNG] (2008 release) Audio Frequency Interference. This movie is played in HSNG Chapter 4. (34 min.) Movie SD Movie HD
Mixed-Signal Isolation: Part II.
HSNG Seminar (2008).
[crosstalk, grounding, mixed signals, SiLab HSNG] (2008 release) RF Crosstalk, RF Cables, and RF Connectors. Parts of this movie are performed live in HSNG Chapters 4 and 6. (33 min.) Movie SD Movie HD
Mixed-Signal Isolation: Part III.
HSNG Seminar (2008).
[crosstalk, grounding, mixed signals, SiLab HSNG] (2008 release) Achieving 120dB Isolation, PCB Traces at RF. This movie is played in HSNG Chapter 6. (29 min.) Movie SD Movie HD
Yao! What a Handshake.
[level translation, termination] Making the output voltage equal VT is the easiest thing in the world for a driver. The terminating voltage is a "natural resting place". If you disconnect the driver, the load immediately relaxes, all by itself, to VT.
[termination, transmission line] A split termination biases the line at a halfway voltage so that the driver need only source or sink enough current to swing the line halfway in either direction.
[attenuation, characteristic impedance, dispersion, transmission line] In the short term, the input impedance of a uniform, lossless, distortionless transmission line appears purely resistive.
[management] Old Aunt Judy approaches you at a reception, with a little halt in her voice, and says, "You know about electronics, right? Well, I’ve got this old 8-track tape player…
VRM Stability - Part I: Feedback.
Newsletter v10_3 (9/10/2007).
[crosstalk, power systems] Feedback must be carefully controlled because, by its very nature, feedback invites the risk of self-oscillation.
Finger the Culprit.
[delay, testing] When debugging a rare mode of failure, never attempt a direct fix. The test cycles associated with each attempted improvement will kill your development schedule. Your first order of business is to make the problem worse.
[EM fields, vias] According to Kirchoff’s laws for circuit analysis, the total inductance of two inductors placed in series should equal the sum of their independent inductances; this is not true for parasitic inductances in high-speed digital circuits.
AC Coupling Layout (for XAUI 3.125 Gb/s).
Newsletter v10_02 (5/18/2007).
[data coding, layout, reflections] The parasitic body capacitance of the AC coupling caps perturbs the characteristic impedance of your transmission line.
Diagnostic Testing (and Tasting).
[management, testing] Diagnostic testing requires a keen awareness of all aspects of the system at hand. The operator must remain ever vigilant during testing, aware of even the tiniest clue about system behavior.
[probes, simulation] Transmission lines, like streets, support traffic in two directions. A voltage probe shows only an aggregate voltage waveform, but doesn’t say which way the waveform is moving.
Newsletter v9_08 (12/21/2006).
[layout, probes, skew] Measuring a tiny time difference like 5 ps can be quite challenging. Anjaly will need well-matched, skew-calibrated probes and perfectly symmetric attachments to the board.
[back plane, bandwidth, testing] Frequency-domain instruments can play an important role in the measurement process, but should not be the main focus of your specification.
Bypass Capacitor Sequencing.
Newsletter 9_07 (10/4/2006).
[bypass capacitors, layout] A trace of any practical length placed in series with the power terminal of a high-speed IC (especially one with multiple VCC pins) radically increases power supply noise at the VCC terminal and should be avoided like the plague.
Voltage Regulator Droop.
[power systems] When the load draws current, the new larger value of regulator output resistance will increase the droop measured at Vcc. That sounds bad, but in some very special circumstances it is actually good for your circuit.
Memory Bus Crosstalk.
Newsletter v9_06 (8/22/2006).
[characteristic impedance, crosstalk, jitter] I am currently working on high speed memory bus with "interconnect jitter". My memory team recommends changing the bus geometry to improve timing.
[ringing, simulation] A PWL edge over-stimulates the resonant behavior. A smooth Gaussian edge better represents a real digital signal, eliminating phantom ripples in your simulation output.
Newsletter v9_05 (6/16/2006).
[bandwidth, reflections, ringing] The Gaussian edge best represents actual digital logic. It displays virtually no perceptible ringing in the time domain—just like the real circuit
[EMC, grounding] Dr. Bruce Archambeault, creator of the IBM EMC rule-checking program "EMSAT", says "Ground is a good place to grow potatoes and carrots", but a poor concept for high-frequency engineering.
[reflections, rise time, termination] I want to force the apparent termination impedance to equal precisely 50 ohms, with minimum degradation of the received signal risetime.
Reason for Ground Split.
Newsletter v9_04 (3/24/2006).
[crosstalk, grounding, split planes] There are indeed applications so sensitive that they require separation of the analog and digital ground regions.
[reflections, rise time, termination] If you can limit the magnitude of the reflections to, say, x percent of the signal swing, then the worst-case time-domain jitter induced by those errant reflected blips will amount to only a x percent of the signal risetime.
Newsletter v9_02 (1/12/2006).
[sampled data, testing] Measurement of low-level analog distortion requires two complementary things: a very good source and a very good instrument for signal detection.
[power dissipation, reflections, termination] (Regarding series termination) a good energy-balance equation often easily sums up the operation of a complicated system without bogging you down in details.
[bypass capacitors] High-Q capacitors exacerbate resonances in a circuit, and resonance is the last thing you need in a power distribution system. Digital folks want low-Q capacitors.
Visible Return Current.
Newsletter v8_08 (12/1/2005).
[returning signal current] I may at last have found a way to demonstrate, in a direct (and dramatic) fashion, to any observer, where and how high-frequency current flows in a printed circuit board.
De-constructing Gain and Impedance from S11.
[attenuation, S-parameters, testing] From measurements of S11, determine both the gain and characteristic impedance of a uniform transmission structure.
Newsletter v8_07 (10/18/2005).
[crosstalk, ground bounce] Do you suppose there is much SSO noise margin left in a typical IC package design? Can you safely exceed the loading guidelines without causing SSO errors? I doubt it.
See Beyond the Edge.
[characteristic impedance, S-parameters, testing] The far-end reflected signal is usually considered the end of usable data in a TDR waveform, but a wealth of information lies beyond this point.
Law of Product Development.
Newsletter v8_06 (10/3/2005).
[attenuation, termination] Regarding attenuating terminations, "The more independant requirements you place on a circuit, the more complex the circuit must become."
Newsletter v8_05 (8/23/2005).
[returning signal current, rise time] Are there really any high-frequency currents still flowing in portions of a transmission line after those portions have been passed over by a voltage disturbance moving down the line?
Millions and Billions.
[back plane, rise time, serial link] When considering any aspect of your circuit geometry, the relation between physical size and risetime helps determine the relative importance of that object in the overall scheme of the circuit.
[management, power systems, transmission line] Engineers enjoy a long tradition of experience with dynamic processes. We have developed over the centuries many diverse means of dealing with them.
[ESD] Design your system to survive near-miss situations. The most common near-miss scenarios include discharges to your product chassis, the wires leading into or out of your chassis, or metallic objects near those wires.
Newsletter v8_04 (5/4/2005).
[chip packaging, EM fields, rise time] The three-dimensional rule for physical scaling of electrical connections immutably controls the performance of connectors, packages, component bodies, vias, and many other common structures.
Newsletter v8_03 (3/1/2005).
[crosstalk, ground bounce] Details, measured lab results, and theory of crosstalk involving hundreds of outputs switching simultaneously in a high-speed Xilinx Virtex-4 FPGA package, as delivered to the Xilinx tech on-line forum March 1, 2005.
Crosstalk - Differential Vias.
Newsletter v8_02 (2/15/2005).
[crosstalk, vias] My CAD tools predict the level of crosstalk from differential digital traces to differential analog traces. That’s fine, but how about the crosstalk from differential digital vias to differential analog vias? How does that work and how big is it?
Crosstalk - Via to Trace.
Newsletter v8_01 (1/25/2005).
[crosstalk, vias] Measurements of crosstalk between an interplane via and an inner-layer trace relevant to the question of minimum separation between a sensitive differential analog pair and a digital via on the same PCB.
DC Blocking Capacitor Value.
Newsletter v7_09 (1/10/2005).
[data coding, level translation, reflections, serial link] How do I choose the value for a DC blocking capacitor in a serial link application?
When Everything Matters.
[management] Squeeze that last drop of performance from a CMOS architecture by turning up the clock or adding a few new features and you may choke on the curse of complexity—where every decision you make interacts with every other decision.
Newsletter v7_10 (12/14/2004).
[data coding, EMC] The improvement in common-mode radiation from the straight, unencoded, worst-case example to the best scrambled-and-coded version is better than 30 dB.
DC Blocking Capacitor Placement.
Newsletter v7_08 (12/12/2004).
[data coding, level translation, reflections, serial link] Slower systems sometimes benefit from placing the DC blocking capacitors close to the source, but not multi-gigabit systems.
Newsletter v7_07 (12/1/2004).
[data coding, serial link] If you are responsible for selecting a serial interface standard, I’d like to pass along a few ideas for your selection criteria, starting with some concepts having to do with the physical link protocol, particularly DC balance.
Jitter and SNR Combined.
Newsletter v7_06 (11/18/2004).
[clocks, jitter] I would rather not consider of the joint probability of occurrence of vertical noise and horizontal jitter in the same equation.
Return Current Matters.
[differential signaling, returning signal current] Differential architectures sometimes tempt us to ignore return current issues… [but] even in a differential configuration, current flows on the planes under each trace separately.
Squeeze Your Layer Stack.
Newsletter v7_04 (9/1/2004).
[back plane, dielectric loss, vias] Given the same trace width and trace impedance, a lower dielectric constant lets you squeeze the layer stack.
[connectors, crosstalk, layer stack, vias] In a multi-layer pcb the vias perform the role of a tiny connector, where the signal-to-ground-via ratio controls via crosstalk.
On-Chip Bypassing with End Terminations.
[bypass capacitors, chip packaging, power systems, termination] On-chip capacitors have no effect on single-ended systems with symmetrically-split end-terminations.
On-Chip Bypassing with Series Terminations.
[bypass capacitors, chip packaging, power systems, termination] On-chip capacitors perform brilliantly in a series-terminated architecture.
Common-mode ground currents.
Newsletter v7_02 (3/24/2004).
[grounding] Instead of thinking of your digital ground region as a solid sheet, think of it as a picture frame. This simple model explains the basis of single-point grounding and many other common-mode noise issues.
Approaching the Edge.
DesignCon 2004 (2/1/2004).
[management, probes] Worst-case budgets don’t work if you don’t include all the necessary factors, or if you make wrong assumptions to fill in gaps in the available data.
Chip Scale Transmission Lines.
Newsletter v7_01 (1/29/2004).
[ringing, termination, transmission line] On-chip interconnections rarely require termination, but pcb traces often do. This conclusion is directly related to the properties of RC and LC transmission lines.
Essential System Margin.
[attenuation, management, serial link] You should make tiny artificially adjustments to every line in the budget until you drive the system margin to zero. Only you will know where these adjustments are hidden.
Parasitic Inductance of Bypass II.
Newsletter v6_09 (12/1/2003).
[bypass capacitors] The following values for the inductance of a surface-mounted bypass capacitor were collected using the step-response technique described in chapter 8 of High-Speed Digital Design.
[connectors, crosstalk, multi level] Connector vendors will soon realize that great improvements in the information-carrying capacity of their products may be had by reducing crosstalk.
Risetime of Lossy Transmission Line.
[cables, rise time] The risetime of a long skin-effect limited cable scales with the square of its length, not according to the sum-of-squares rule for [the risetime of] cascaded linear systems.
[clocks, overshoot, skew] Ernie reduces the value of his series terminator, inducing some intentional overshoot that partially compensates for the lack of vivre in the received signal and speeding up (slightly) the threshold crossing.
Relevance of Physics.
[electromigration, management, power dissipation] The engineering curriculum for first-year students at Oxford University still includes a good amount of basic physics, despite attempts by computer scientists at other universities to de-emphasize that subject.
Short-Term Impedance of Planes.
Newsletter v6_05 (3/24/2003).
[EM fields, power systems, returning signal current, vias] Doesn’t the returning signal current just pop between the planes through the parasitic capacitance of the planes themselves, you might ask?
Why Johnny Can’t Design a High-Speed Digital System.
DesignCon 2003 (2/17/2003).
[management] As a class, digital engineers are less well equipped now than they were 30 years ago to design a high-speed digital system.
Bypass Capacitor Array.
Newsletter v6-02 (1/24/2003).
[bypass capacitors, power systems] This spreadsheet produces a beautiful color version of my figure 8.9 showing the impedance of each element of a power system and also the composite impedance of all four elements taken in parallel.
Reducing EMI with Differential Signaling.
[differential signaling, EMC] You need not struggle to place ordinary differential digital traces any closer than 0.5 mm for any EMI purpose.
Differential Receivers Tolerate High-Frequency Losses.
[attenuation, differential signaling, dispersion, serial link] Differential receivers have more accurate switching thresholds than ordinary single-ended logic.
Asymmetry in Broadside Configuration.
[differential signaling, layer stack, layout, skew] In general I avoid broadside-coupled traces unless they are made necessary by routing considerations.
[differential signaling, EMC] Any imbalanced circuit element within an otherwise well-balanced transmission channel creates a region of partial coupling between the differential and common modes of transmission at that point.
Characteristic Impedance of Lossy Line.
[characteristic impedance, dielectric loss, skin effect] Skin-effect losses increase the real part of the impedance curve in the vicinity of the skin-effect onset, while the dielectric losses decrease the real part of impedance in the same area.
Mixtures of skin-effect and dielectric loss.
[dielectric loss, dispersion, skin effect] Long, high-speed pcb traces operate in a zone influenced by both skin-effect and dielectric losses. Both mechanisms attenuate the high-frequency portion of your signals, but in slightly different ways.
Capacitor Layout Matters.
[bypass capacitors, layout, power systems] Your problem is likely caused by the layout, which has more than tripled the inductance of each bypass capacitor, not the values of types of capacitance.
Random and Deterministic Jitter.
[clocks, jitter] The point of separating jitter into random and deterministic components is that the deterministic components have a lower ratio of peak value to standard deviation than do the random components.
Passivation and Solder Mask.
[attenuation, microstrip, skin effect] Copper traces on outer layers must be protected from corrosion by passivation or by coating them with an inert material.
[simulation] Spice is grand for non-linear circuits, but if your circuit is linear you might question whether it is best. The FFT shines as an efficient computational tool for long transmission channels.
[differential signaling, skew] Two strategies for minimizing the intra-pair skew accumulated by a differential net: (1) A pair that starts and ends going north has by definition equal numbers of right and left-hand turns. (2) How your layout enters or leaves a BGA makes a difference.
Newsletter v5-6 (4/22/2002).
[attenuation, skin effect] We have been advised that due to the changes to the skin effect caused by the Ni/Au on the traces for high frequency RF designs we could be building in a problem.
A transmission line is always a transmission line.
[characteristic impedance, reflections, transmission line] Does the input impedance behave one way on a long transmission line but differently when the load is adjacent to the driver? How does it know what to do?
SONET data coding.
Newsletter v5-5 (3/29/2002).
[data coding, level translation] Figure 1 shows one way to build a non-linear DC restorer. This circuit fixes the DC balance of a SONET data string that has lost its DC level because of AC-coupling.
Steel-plated Power Planes.
[power systems, reference planes] A thin coating of steel, applied to the inside-facing surfaces of a power and ground plane pair may help damp power plane resonance.
[proximity effect, simulation, skin effect, transmission line] You can model the proximity effect (and see edge-current concentration) using a simple model made from a sheet of rubber and a popsicle stick.
ESR of Regulator Output Capacitor.
Newsletter v5-3 (2/25/2002).
[bypass capacitors, management, power systems] How can the ESR of a bulk capacitor (tantalum or electrolytic capacitor) affect a linear voltage regulator?
[grounding, probes] All good probes come with short, tiny ground attachments. For single-ended measurements, don’t depend on mysterious ground connections. Always use a good, short ground connection.
Differential (Microstrip) Trace Impedance.
Newsletter v5-2 (1/22/2002).
[characteristic impedance, differential signaling] Many different combinations of height, width and spacing can generate the same differential impedance.
Value of End Terminator.
Newsletter v5-1 (1/7/2002).
[EMC, termination] Should an end-terminator always be set at the highest value that works because that minimizes the current and therefore gives the best EMI performance?
Accurate Series Termination.
Newsletter v4-14 (11/1/2001).
[termination] How are you supposed to calculate an appropriate series termination when you have such a large variance in the source impedance of the driver?
Nasty ESD Testing.
Newsletter v4-13 (10/24/2001).
[ESD, testing] A thin, plastic package sitting on a metal desk, with wires hanging out the back of the package will prove embarrassingly susceptible to ESD.
Proximity Effect III.
Newsletter v4-8 (10/3/2001).
[crosstalk, high-speed design formulas, proximity effect, returning signal current] Justification for crosstalk approximation (see High-Speed Digital Design p. 190, eqn. [5.1])
[testing] Debugging new hardware can be difficult and trying. The most common mistakes that most new engineers make when first debugging a system are: trying to debug too much at once, not testing their assumptions, and keeping inadequate records.
So Good it Works on Barbed Wire.
[cables, transmission line] Next time you look at a transmission line, I hope you’ll focus on the big four properties: characteristic impedance, high-frequency loss, delay, and crosstalk.
Dielectric Loss Tangents.
Newsletter v4-5 (6/11/2001).
[attenuation, dielectric loss] For a capacitor formed from a lossy dielectric material, the loss tangent is the ratio at any particular frequency between the real and imaginary parts of the impedance of the capacitor.
[management] Scotty to Kirk, "We cannot get the shields back in less than an hour, Captain. The Klingon attack cracked our DiLithium crystal, and there’s antimatter leaking everywhere…"
Proximity Effect II.
Newsletter v4-3 (6/1/2001).
[proximity effect, returning signal current, skin effect] Do you have any references dealing… with the current density distribution in a ground plane under a high frequency signal trace?
[connectors, crosstalk, testing] I would like to replace one connector type with a different, less expensive model. How do I prove the two connectors have the same electrical characteristics?
[EMC, termination] Most radiated emissions problems depend more on signal currents than signal voltages. The source-termination resistance controls both received signal amplitude and drive current.
[clocks, delay, skew] If you are using some form of delay line to match clock delays at all points of usage within a pc board, here’s a short list of the items you need to match:
Breaking Up a Pair.
[layout, reflections, stripline] The two traces comprising a differential pair, when routed close together, share a certain amount of cross-coupling. This coupling lowers the differential impedance between the traces.
[power systems] With electromagnetic noise present, you can talk sensibly about potential differences only between points that are co-located, that is, points so close that the total field strength between those points is negligible.
Parasitic Inductance of Bypass Capacitors.
[bypass capacitors, layout] You can estimate the parasitic series inductance of a bypass capacitor in a multi-layer board with solid power and ground planes.
(The) Way Home.
[bypass capacitors, layout] Current always makes a loop. If it goes out, it must find a way back home. The shapes of both the outgoing and the return paths affect the observed inductance.
Who’s Afraid of the Big, Bad Bend?.
[microstrip, reflections, transmission line] Right-angle bends in PC-board traces perform perfectly well in digital designs in speeds as fast as 2 Gbps.
Newsletter v4-1 (3/10/2000).
[proximity effect, returning signal current, skin effect] Is there a "Proximity Effect" in strip lines or microstrips that is caused by currents flowing in adjacent conductors?
[metastability] Without clearly quantified limits on the "acceptable probability of failure," you never know whether you have implemented too little or too much of your favorite failure-rate cure.
(The) Future of On-Chip Interconnections.
[interconnections, multi level] Today’s chip-layout software takes into account the RC propagation delays of major bus structures and clock lines. In tomorrow’s designs, at even higher speeds, the full RLC nature of the on-chip transmission channels will emerge.
Multi-Level Signaling -- Designcon2000.
DesignCon 2000 (1/30/2000).
[back plane, multi level, serial link] multi-amplitude signaling won’t help much below 2.5 Gb/s, however, at higher speeds where the loss slope increases MAS becomes very useful.
[EMC] Keeping your traces close to a solid, uninterrupted reference plane is one of simplest, most effective things you can do to reduce electromagnetic radiation and harden your product against ESD.
Newsletter v3-21 (8/30/1999).
[layer stack, power systems, returning signal current] Follow-up to "High-Speed Return Signals" newsletter v1-15, discusses the effective useful radius of the interplane capacitance.
Dual Ground Shields.
Newsletter v3-19 (8/12/1999).
[layer stack, reference planes] Theoretically, if the planes are completely solid (no holes), they would act as near-perfect isolation boundaries, BUT you have to consider the holes…
[clocks, EMC, jitter] Is there any way to make a timing reference that has low jitter and low spectral peaks and at the same time is compatible with zero-delay-repeater structures?
Point to Point Wiring and Big Loads.
Newsletter v3-16 (7/21/1999).
[reflections, ringing, wire wrap] Your best choices are to either slow down the driver risetime a little bit so the whole thing acts as one big lumped-element circuit, or use a real 75-ohm transmission line.
[interconnections] When you look at a digital machine, if you are not looking at the interconnections, you are missing one of the most important parts of the structure.
Differential Signaling (Through Connectors).
Newsletter v3-12 (5/7/1999).
[differential signaling] I have 16 differential line pairs that have to go through a connector. What signal to ground ratio and pattern should I use?
Crosstalk and SSO Noise.
Newsletter v3-9 (3/30/1999).
[crosstalk, ground bounce] What you need is a simple experiment that will separate the effects of SSN (simultaneous switching noise) from other crosstalk.
Newsletter v3-8 (3/23/1999).
[transmission line] Can you give me a basic (approximate) formula for the inductance of (1) a bare pc trace, and (2) A trace suspended above an adjacent plane.
Severe Overshoot Mailbag.
Newsletter v3-1 (1/14/1999).
[overshoot, ringing] ...the clamp diodes shot current into the VCC net… …make sure you are measuring the overshoot correctly… ...Undershoot on some lines on some SRAM chips will cause "weak writes"…
Signal Ground Drain Wire.
Newsletter v2-32 (12/4/1998).
[cables, connectors, EMC, ground bounce] Why should disconnecting the "drain wire" at the connectors have such a drastic impact on the rise/fall time of the outer conductors?
Delay Through Via.
Newsletter v2-29 (10/29/1998).
[delay, vias] For vias which traverse several planes, the delay is a function not only of the via but also of the position and configuration of nearby bypass capacitors.
Measuring Power-Plane Resonance.
Newsletter v2-27 (10/15/1998).
[power systems] James Mears of National Semiconductor describes his experience attempting to measure the impedance between power-and-ground planes.
Newsletter v2-24 (9/9/1998).
[power dissipation, termination] The promise of an AC terminator is the idea that maybe, just maybe, there is a value of C big enough to make a good termination, but at the same time small enough to not draw much current from the source.
Newsletter v2-21 (8/17/1998).
[differential signaling, reflections, transmission line] Does the standard formula for reflections also apply to differential/balanced lines where two lines carry one signal?
Intentional Clock Modulation.
[clocks, EMC, jitter] Over the years, various techniques have been proposed for modulating, or dithering, the clock frequency to break up the accumulated spectral power into a larger number of new modes.
Segmenting the Vcc Plane.
Newsletter v2-18 (7/23/1998).
[EMC, ferrite beads, power systems] I don’t cut up the Vcc plane unless I have one circuit that is substantially more sensitive to Vcc noise than the other circuits on the board.
Radiated Digital Ground Noise.
Newsletter v2-17 (6/26/1998).
[EMC, grounding] Ideally, you should ground your digital logic, the chassis, any cable grounds, and the cable shield (if present) to a common point.
Newsletter v2-15 (6/4/1998).
[interconnections, system-on-a-chip] A reader suggests, "The days of discrete design and interconnect are rapidly disappearing, if not gone already."
Measuring Power-Ground Impedance.
Newsletter v2-14 (5/26/1998).
[power systems] How to convert network-analyzer measurements of the impedance between a pair of power-and-ground planes from dB to ohms. Suggestions on probe configuration.
Keeping Up With Moore.
[management] multi-layer pc-boards, solid power and ground planes, surface-mount technology, reflow soldering, and the BGA package were the prominent advances in packaging during the last 20 years.
EMI Simulations Tools.
[EMC, simulation] (Originally titled: EMI Simulation Tools) Many EMI simulators are embellished with flashy demonstrations, which, like the smell of coffee brewing, or the sound of bacon frying, promise more than they can possibly deliver.
Why Digital Engineers Don’t Believe in EMC.
EMC Soc nwsltr (3/2/1998).
[EMC] Digital engineers don’t believe current flows in loops, existence of the H-field, gates are differential amplifiers, existence of EM waves, or that EMC will advance their careers
Newsletter v2-5 (2/9/1998).
[open drain, termination] Should I use one pull-up resistor located somewhere in the middle of my line, or two resistors of twice the value located at each end?
Power-Ground Source Impedance.
Newsletter v2-4 (1/30/1998).
[power systems] This reader takes issue with my claim of having achieved a power-to-ground impedance of 0.01 ohms by paralleling one hundred 0.1uF caps, each having 1 ohm or less impedance at the frequencies of interest.
Cable Shield Grounding.
Newsletter v2-2 (1/16/1998).
[cables, connectors, EMC, grounding] Joe, I am going to disagree with your suggestion that a shield with a resistor at one end acts as an effective EMI shield. In high-speed digital applications, it doesn’t.
Tricky DRAM Lines.
Newsletter v1-20 (12/15/1997).
[layout, multi drop, split planes] The app note I’m looking at suggests that my DRAM address lines run in a "T" shape… with a ground plane cut under the DRAMs
Transmission Lines/Gate Delay.
Newsletter v1-19 (12/4/1997).
[transmission line] What does this mean: "Until the driver becomes aware of the impedance mismatch at the end of the line the line looks resistive"
Another Version of a Coax Probe.
Newsletter v1-18 (11/26/1997).
[probes] What kind of probes do I need for looking at noise (<100 mV to 300 mV range) on the various ground pins of some gigabit transceivers?
Bypass Multi-Valued Arrays.
Newsletter v1-17 (11/14/1997).
[bypass capacitors, power systems] I discourage engineers from combining together different-valued capacitors if they share the same package format.
Newsletter v1-16 (11/4/1997).
[EMC, simulation] What are the primary issues at hand, and what are the important questions to ask before you get yourself mired in a project that may not pay off.
Ringing in a New Era.
[ringing, simulation] From this day forward there is absolutely, completely, totally no longer any excuse whatsoever for system problems, glitches, data errors or other artifacts related to ringing in digital signals.
Newsletter v1-11 (9/15/1997).
[high-speed design formulas, power systems] Regarding page 414, equation for calculating the DC resistance of power planes based on the diameters of two contact points space at X amount of distance.
Power Bus Noise.
Newsletter v1-9 (8/26/1997).
[power dissipation, power systems] The CMOS devices that we have looked at can draw peak currents of about an Amp from the power bus (when a single gate switches) if they are connected with a sufficiently low inductance.
Directionality of Crosstalk.
[crosstalk, layout] (Originally titled: The Real Truth About Crosstalk) If you are trying to manage crosstalk from first principles, so it comes out right on the first spin, look into the new crosstalk prediction tools that feature IBIS I/O modeling.
(The) Real Truth About Crosstalk.
[crosstalk, layout] If you are trying to manage crosstalk from first principles, so it comes out right on the first spin, look into the new crosstalk prediction tools that feature IBIS I/O modeling.
Newsletter v1-8 (8/15/1997).
[grounding, layer stack, power systems] At very high speeds, bypass capacitance needs to be within less than 1/10 of a rising-edge-length in order to function effectively.
Bypass Capacitor Layout.
[bypass capacitors, layout, power systems] The primary symptoms of an inadequate, old-fashioned bypass capacitor array are increased power supply noise, increased crosstalk among signal traces, and increased electro-magnetic radiation.
Tips on Controlling Clock Skew.
[clocks, skew] Your ability to manage and control clock skew has been recently improved by the introduction of a new generation of multi-output, low-skew clock drivers.
Newsletter v1-5 (7/14/1997).
[differential signaling, termination] I thought that PECL outputs always need external resistors to ground since PECL drivers can only source current but not sink it.
PCI Series Terminations Resistors.
Newsletter v1-4 (7/4/1997).
[delay, multi drop, PCI] It’s OK to use series termination resistors with bi-directional transceivers. The series resistor just delays the incoming signals and degrades their risetimes.
Newsletter v1-3 (6/24/1997).
[EMC, grounding, reference planes] The "poured ground" (more commonly called a "ground fill") is a technique useful on two-layer boards for reducing crosstalk due to ELECTRIC FIELD coupling. Superceded by "Ground Fill", EDN 26 May 2005.
Planning For Signal Integrity.
[ringing, simulation] At these extremes of speed, even simple problems, like ringing, can become complex. Check out the nifty new simulation tools now available for dealing with signal integrity problems.
Operating Above Resonance.
[bypass capacitors, layout] It’s OK to use a bypass capacitor well above its point of series-resonance. That’s the normal mode of operation for most bypass capacitors.
[simulation] IBIS is going to solve a lot of common, everyday, high-speed design problems, but, first we have to get our chip vendors to provide IBIS model files for every part they make.
Probing High-Speed Digital Designs.
[probes] In high-speed system developments, the ubiquitous 10-pF 10:1 capacitive-input probe is no longer adequate. The two alternatives are the FET-input probe and the resistive-input probe.
[clocks, jitter] If you are using a clock multiplier, or a PLL-based clock regenerator, make sure to comply with the specifications for offset, wander, and jitter on the reference clock input.
[Ernie, management] Engineers without a basic understanding of high-speed effects will likely end up just like Ernie, sitting in somebody else’s office, fidgeting and sweating.
(The) Curse of FAST Logic.
[power dissipation, rise time] Your circuits fill a motherboard, not a whole room, but still fall prey to the same signal propagation difficulties encountered in 1946 by Mauchly and Eckert on the ENIAC project.
IBIS Simulation with Gaussian Edges.
HSDD Seminar: 2.29-2.33.
[rise time, simulation] Simulation artifacts caused by the use of piecewise-linear (PWL) Spice sources. Presentation of Gaussian source useful for eliminating the artifacts.